diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2012-05-31 19:00:25 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-06-01 12:00:14 -0400 |
commit | 416a2bd274566a6f607a271f524b2dc0b84d9106 (patch) | |
tree | 502720262c07cdb14bc14155bc8295cc20a7d411 /drivers/gpu/drm/radeon/evergreend.h | |
parent | 95c4b23ec4e2fa5604df229ddf134e31d7b3b378 (diff) |
drm/radeon: fixup tiling group size and backendmap on r6xx-r9xx (v4)
Tiling group size is always 256bits on r6xx/r7xx/r8xx/9xx. Also fix and
simplify render backend map. This now properly sets up the backend map
on r6xx-9xx which should improve 3D performance.
Vadim benchmarked also:
Some benchmarks on juniper (5750), fullscreen 1920x1080,
first result - kernel 3.4.0+ (fb21affa), second - with these patches:
Lightsmark: 91 fps => 123 fps +35%
Doom3: 74 fps => 101 fps +36%
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 3dd43e760362..2773039b4902 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -37,6 +37,15 @@ | |||
37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF | 37 | #define EVERGREEN_MAX_PIPES_MASK 0xFF |
38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF | 38 | #define EVERGREEN_MAX_LDS_NUM 0xFFFF |
39 | 39 | ||
40 | #define CYPRESS_GB_ADDR_CONFIG_GOLDEN 0x02011003 | ||
41 | #define BARTS_GB_ADDR_CONFIG_GOLDEN 0x02011003 | ||
42 | #define CAYMAN_GB_ADDR_CONFIG_GOLDEN 0x02011003 | ||
43 | #define JUNIPER_GB_ADDR_CONFIG_GOLDEN 0x02010002 | ||
44 | #define REDWOOD_GB_ADDR_CONFIG_GOLDEN 0x02010002 | ||
45 | #define TURKS_GB_ADDR_CONFIG_GOLDEN 0x02010002 | ||
46 | #define CEDAR_GB_ADDR_CONFIG_GOLDEN 0x02010001 | ||
47 | #define CAICOS_GB_ADDR_CONFIG_GOLDEN 0x02010001 | ||
48 | |||
40 | /* Registers */ | 49 | /* Registers */ |
41 | 50 | ||
42 | #define RCU_IND_INDEX 0x100 | 51 | #define RCU_IND_INDEX 0x100 |
@@ -54,6 +63,7 @@ | |||
54 | #define BACKEND_DISABLE(x) ((x) << 16) | 63 | #define BACKEND_DISABLE(x) ((x) << 16) |
55 | #define GB_ADDR_CONFIG 0x98F8 | 64 | #define GB_ADDR_CONFIG 0x98F8 |
56 | #define NUM_PIPES(x) ((x) << 0) | 65 | #define NUM_PIPES(x) ((x) << 0) |
66 | #define NUM_PIPES_MASK 0x0000000f | ||
57 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) | 67 | #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) |
58 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) | 68 | #define BANK_INTERLEAVE_SIZE(x) ((x) << 8) |
59 | #define NUM_SHADER_ENGINES(x) ((x) << 12) | 69 | #define NUM_SHADER_ENGINES(x) ((x) << 12) |