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authorAlex Deucher <alexdeucher@gmail.com>2010-03-24 13:36:43 -0400
committerDave Airlie <airlied@redhat.com>2010-04-08 20:16:04 -0400
commitfe251e2fffa1ebc17c8e6e895b0374ae4e732fa5 (patch)
tree995060a10005d4a284bebcd0412fabfd0805de89 /drivers/gpu/drm/radeon/evergreend.h
parent32fcdbf4084544c3d8fa413004d57e5dc6f2eefe (diff)
drm/radeon/kms/evergreen: setup and enable the CP
The command processor (CP) fetches command buffers and feeds the GPU. This patch requires the evergreen family me and pfp ucode files. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index effe335356c7..10e9768534da 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -89,6 +89,7 @@
89#define CP_QUEUE_THRESHOLDS 0x8760 89#define CP_QUEUE_THRESHOLDS 0x8760
90#define ROQ_IB1_START(x) ((x) << 0) 90#define ROQ_IB1_START(x) ((x) << 0)
91#define ROQ_IB2_START(x) ((x) << 8) 91#define ROQ_IB2_START(x) ((x) << 8)
92#define CP_RB_BASE 0xC100
92#define CP_RB_CNTL 0xC104 93#define CP_RB_CNTL 0xC104
93#define RB_BUFSZ(x) ((x) << 0) 94#define RB_BUFSZ(x) ((x) << 0)
94#define RB_BLKSZ(x) ((x) << 8) 95#define RB_BLKSZ(x) ((x) << 8)
@@ -104,6 +105,7 @@
104#define CP_RB_WPTR_ADDR_HI 0xC11C 105#define CP_RB_WPTR_ADDR_HI 0xC11C
105#define CP_RB_WPTR_DELAY 0x8704 106#define CP_RB_WPTR_DELAY 0x8704
106#define CP_SEM_WAIT_TIMER 0x85BC 107#define CP_SEM_WAIT_TIMER 0x85BC
108#define CP_DEBUG 0xC1FC
107 109
108 110
109#define GC_USER_SHADER_PIPE_CONFIG 0x8954 111#define GC_USER_SHADER_PIPE_CONFIG 0x8954