drm/radeon/kms/evergreen: set the clear state to the blit state

The hw stores a default clear state for registers in the context
range that can be initialized when the CP is set up.  Set the
blit state as the default clear state and use the CLEAR_STATE
packet to load the blit state rather than loading it from an IB.
This reduces overhead when doing bo moves using the 3D engine.

Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index d507f438eed0..113c70cc8b39 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -658,6 +658,8 @@
 #define PACKET3_EVENT_WRITE_EOP                         0x47
 #define PACKET3_EVENT_WRITE_EOS                         0x48
 #define PACKET3_PREAMBLE_CNTL                           0x4A
+#              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
+#              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
 #define PACKET3_RB_OFFSET                               0x4B
 #define PACKET3_ALU_PS_CONST_BUFFER_COPY                0x4C
 #define PACKET3_ALU_VS_CONST_BUFFER_COPY                0x4D