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authorAlex Deucher <alexander.deucher@amd.com>2013-10-10 18:03:06 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-11-01 12:43:20 -0400
commitb18802588809d6ff20db762ddcadb0dbe1f46414 (patch)
treeaab5d9a5cd993030a9063e7b1d9f73fd683756c8 /drivers/gpu/drm/radeon/evergreen_hdmi.c
parent712fd8a2cdc4360b14546a26ce238bd99661af51 (diff)
drm/radeon/audio: write audio/video latency info for DCE6/8
Needed by the hda driver to properly set up synchronization on the audio side. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_hdmi.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index abdc893318a4..678736542ed8 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -35,6 +35,8 @@
35extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder); 35extern void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder);
36extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder); 36extern void dce6_afmt_write_sad_regs(struct drm_encoder *encoder);
37extern void dce6_afmt_select_pin(struct drm_encoder *encoder); 37extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
38extern void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
39 struct drm_display_mode *mode);
38 40
39/* 41/*
40 * update the N and CTS parameters for a given pixel clock rate 42 * update the N and CTS parameters for a given pixel clock rate
@@ -361,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
361 if (ASIC_IS_DCE6(rdev)) { 363 if (ASIC_IS_DCE6(rdev)) {
362 dce6_afmt_select_pin(encoder); 364 dce6_afmt_select_pin(encoder);
363 dce6_afmt_write_sad_regs(encoder); 365 dce6_afmt_write_sad_regs(encoder);
366 dce6_afmt_write_latency_fields(encoder, mode);
364 } else { 367 } else {
365 evergreen_hdmi_write_sad_regs(encoder); 368 evergreen_hdmi_write_sad_regs(encoder);
366 dce4_afmt_write_latency_fields(encoder, mode); 369 dce4_afmt_write_latency_fields(encoder, mode);