diff options
author | Rafał Miłecki <zajec5@gmail.com> | 2012-05-06 11:29:45 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2012-05-13 09:19:36 -0400 |
commit | 1c3439f228db0f9b81111752a1d009d26a8ba47e (patch) | |
tree | cfbde31b5396eebc1e0c6f2bbd0d5571b9eb918e /drivers/gpu/drm/radeon/evergreen_hdmi.c | |
parent | e55d3e6cb691ee71b905ce24461940d77bc3833b (diff) |
drm/radeon/hdmi: update modesetting
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen_hdmi.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen_hdmi.c | 43 |
1 files changed, 32 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c index d3d00b56b0d3..e221f15bb489 100644 --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c | |||
@@ -158,30 +158,51 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode | |||
158 | 158 | ||
159 | r600_audio_set_clock(encoder, mode->clock); | 159 | r600_audio_set_clock(encoder, mode->clock); |
160 | 160 | ||
161 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, | ||
162 | HDMI_NULL_SEND); /* send null packets when required */ | ||
163 | |||
161 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); | 164 | WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); |
162 | WREG32(HDMI_GC + offset, 0x0); | ||
163 | 165 | ||
164 | /* Send audio packets */ | 166 | WREG32(HDMI_AUDIO_PACKET_CONTROL + offset, |
165 | WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, | 167 | HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */ |
166 | AFMT_AUDIO_SAMPLE_SEND, ~AFMT_AUDIO_SAMPLE_SEND); | 168 | HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */ |
167 | 169 | ||
168 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, 0x1000); | 170 | WREG32(AFMT_AUDIO_PACKET_CONTROL + offset, |
171 | AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */ | ||
172 | AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */ | ||
169 | 173 | ||
170 | evergreen_hdmi_update_ACR(encoder, mode->clock); | 174 | WREG32(HDMI_ACR_PACKET_CONTROL + offset, |
175 | HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */ | ||
176 | HDMI_ACR_SOURCE); /* select SW CTS value */ | ||
177 | |||
178 | WREG32(HDMI_VBI_PACKET_CONTROL + offset, | ||
179 | HDMI_NULL_SEND | /* send null packets when required */ | ||
180 | HDMI_GC_SEND | /* send general control packets */ | ||
181 | HDMI_GC_CONT); /* send general control packets every frame */ | ||
182 | |||
183 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, | ||
184 | HDMI_AVI_INFO_SEND | /* enable AVI info frames */ | ||
185 | HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */ | ||
186 | HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ | ||
187 | HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ | ||
171 | 188 | ||
172 | WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 0x13); | 189 | WREG32(AFMT_INFOFRAME_CONTROL0 + offset, |
190 | AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ | ||
173 | 191 | ||
174 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 0x202); | 192 | WREG32(HDMI_INFOFRAME_CONTROL1 + offset, |
193 | HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */ | ||
194 | HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ | ||
195 | |||
196 | WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ | ||
175 | 197 | ||
176 | evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | 198 | evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
177 | 0, 0, 0, 0, 0, 0); | 199 | 0, 0, 0, 0, 0, 0); |
178 | 200 | ||
201 | evergreen_hdmi_update_ACR(encoder, mode->clock); | ||
202 | |||
179 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ | 203 | /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ |
180 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); | 204 | WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); |
181 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); | 205 | WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF); |
182 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); | 206 | WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); |
183 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); | 207 | WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); |
184 | |||
185 | /* audio packets per line, does anyone know how to calc this ? */ | ||
186 | WREG32_P(AFMT_AUDIO_PACKET_CONTROL + offset, 0x00040000, ~0x001F0000); | ||
187 | } | 208 | } |