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authorDave Airlie <airlied@redhat.com>2010-04-19 23:16:50 -0400
committerDave Airlie <airlied@redhat.com>2010-04-19 23:16:50 -0400
commit153549b8b63d71a9c5d8cbde887097b995c32bd6 (patch)
tree306ece7479bb98172272013dd02b243e6677a3f4 /drivers/gpu/drm/radeon/evergreen.c
parent7fff400be6fbf64f10abca9939718aaf1d61c255 (diff)
parenta7433742d62c6e0e1173bd144a4aef7724b48d60 (diff)
Merge branch 'drm-radeon-evergreen-accel' into drm-core-next
* drm-radeon-evergreen-accel: drm/radeon: fix cypress firmware typo. drm/radeon/kms/evergreen: add hpd support drm/radeon/kms/evergreen: implement irq support drm/radeon/kms/evergreen: setup and enable the CP drm/radeon/kms/evergreen: implement gfx init drm/radeon/kms/evergreen: add soft reset function drm/radeon/kms/evergreen: add gart support drm/radeon/kms: add support for evergreen power tables drm/radeon/kms: update atombios.h power tables for evergreen
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c1483
1 files changed, 1431 insertions, 52 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index bd1bb9fb2b2a..3295154e5934 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -28,39 +28,194 @@
28#include "radeon.h" 28#include "radeon.h"
29#include "radeon_asic.h" 29#include "radeon_asic.h"
30#include "radeon_drm.h" 30#include "radeon_drm.h"
31#include "rv770d.h" 31#include "evergreend.h"
32#include "atom.h" 32#include "atom.h"
33#include "avivod.h" 33#include "avivod.h"
34#include "evergreen_reg.h" 34#include "evergreen_reg.h"
35 35
36#define EVERGREEN_PFP_UCODE_SIZE 1120
37#define EVERGREEN_PM4_UCODE_SIZE 1376
38
36static void evergreen_gpu_init(struct radeon_device *rdev); 39static void evergreen_gpu_init(struct radeon_device *rdev);
37void evergreen_fini(struct radeon_device *rdev); 40void evergreen_fini(struct radeon_device *rdev);
38 41
39bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) 42bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
40{ 43{
41 bool connected = false; 44 bool connected = false;
42 /* XXX */ 45
46 switch (hpd) {
47 case RADEON_HPD_1:
48 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
49 connected = true;
50 break;
51 case RADEON_HPD_2:
52 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
53 connected = true;
54 break;
55 case RADEON_HPD_3:
56 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
57 connected = true;
58 break;
59 case RADEON_HPD_4:
60 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
61 connected = true;
62 break;
63 case RADEON_HPD_5:
64 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
65 connected = true;
66 break;
67 case RADEON_HPD_6:
68 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
69 connected = true;
70 break;
71 default:
72 break;
73 }
74
43 return connected; 75 return connected;
44} 76}
45 77
46void evergreen_hpd_set_polarity(struct radeon_device *rdev, 78void evergreen_hpd_set_polarity(struct radeon_device *rdev,
47 enum radeon_hpd_id hpd) 79 enum radeon_hpd_id hpd)
48{ 80{
49 /* XXX */ 81 u32 tmp;
82 bool connected = evergreen_hpd_sense(rdev, hpd);
83
84 switch (hpd) {
85 case RADEON_HPD_1:
86 tmp = RREG32(DC_HPD1_INT_CONTROL);
87 if (connected)
88 tmp &= ~DC_HPDx_INT_POLARITY;
89 else
90 tmp |= DC_HPDx_INT_POLARITY;
91 WREG32(DC_HPD1_INT_CONTROL, tmp);
92 break;
93 case RADEON_HPD_2:
94 tmp = RREG32(DC_HPD2_INT_CONTROL);
95 if (connected)
96 tmp &= ~DC_HPDx_INT_POLARITY;
97 else
98 tmp |= DC_HPDx_INT_POLARITY;
99 WREG32(DC_HPD2_INT_CONTROL, tmp);
100 break;
101 case RADEON_HPD_3:
102 tmp = RREG32(DC_HPD3_INT_CONTROL);
103 if (connected)
104 tmp &= ~DC_HPDx_INT_POLARITY;
105 else
106 tmp |= DC_HPDx_INT_POLARITY;
107 WREG32(DC_HPD3_INT_CONTROL, tmp);
108 break;
109 case RADEON_HPD_4:
110 tmp = RREG32(DC_HPD4_INT_CONTROL);
111 if (connected)
112 tmp &= ~DC_HPDx_INT_POLARITY;
113 else
114 tmp |= DC_HPDx_INT_POLARITY;
115 WREG32(DC_HPD4_INT_CONTROL, tmp);
116 break;
117 case RADEON_HPD_5:
118 tmp = RREG32(DC_HPD5_INT_CONTROL);
119 if (connected)
120 tmp &= ~DC_HPDx_INT_POLARITY;
121 else
122 tmp |= DC_HPDx_INT_POLARITY;
123 WREG32(DC_HPD5_INT_CONTROL, tmp);
124 break;
125 case RADEON_HPD_6:
126 tmp = RREG32(DC_HPD6_INT_CONTROL);
127 if (connected)
128 tmp &= ~DC_HPDx_INT_POLARITY;
129 else
130 tmp |= DC_HPDx_INT_POLARITY;
131 WREG32(DC_HPD6_INT_CONTROL, tmp);
132 break;
133 default:
134 break;
135 }
50} 136}
51 137
52void evergreen_hpd_init(struct radeon_device *rdev) 138void evergreen_hpd_init(struct radeon_device *rdev)
53{ 139{
54 /* XXX */ 140 struct drm_device *dev = rdev->ddev;
141 struct drm_connector *connector;
142 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
143 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
144
145 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
146 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
147 switch (radeon_connector->hpd.hpd) {
148 case RADEON_HPD_1:
149 WREG32(DC_HPD1_CONTROL, tmp);
150 rdev->irq.hpd[0] = true;
151 break;
152 case RADEON_HPD_2:
153 WREG32(DC_HPD2_CONTROL, tmp);
154 rdev->irq.hpd[1] = true;
155 break;
156 case RADEON_HPD_3:
157 WREG32(DC_HPD3_CONTROL, tmp);
158 rdev->irq.hpd[2] = true;
159 break;
160 case RADEON_HPD_4:
161 WREG32(DC_HPD4_CONTROL, tmp);
162 rdev->irq.hpd[3] = true;
163 break;
164 case RADEON_HPD_5:
165 WREG32(DC_HPD5_CONTROL, tmp);
166 rdev->irq.hpd[4] = true;
167 break;
168 case RADEON_HPD_6:
169 WREG32(DC_HPD6_CONTROL, tmp);
170 rdev->irq.hpd[5] = true;
171 break;
172 default:
173 break;
174 }
175 }
176 if (rdev->irq.installed)
177 evergreen_irq_set(rdev);
55} 178}
56 179
57 180void evergreen_hpd_fini(struct radeon_device *rdev)
58void evergreen_bandwidth_update(struct radeon_device *rdev)
59{ 181{
60 /* XXX */ 182 struct drm_device *dev = rdev->ddev;
183 struct drm_connector *connector;
184
185 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
186 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
187 switch (radeon_connector->hpd.hpd) {
188 case RADEON_HPD_1:
189 WREG32(DC_HPD1_CONTROL, 0);
190 rdev->irq.hpd[0] = false;
191 break;
192 case RADEON_HPD_2:
193 WREG32(DC_HPD2_CONTROL, 0);
194 rdev->irq.hpd[1] = false;
195 break;
196 case RADEON_HPD_3:
197 WREG32(DC_HPD3_CONTROL, 0);
198 rdev->irq.hpd[2] = false;
199 break;
200 case RADEON_HPD_4:
201 WREG32(DC_HPD4_CONTROL, 0);
202 rdev->irq.hpd[3] = false;
203 break;
204 case RADEON_HPD_5:
205 WREG32(DC_HPD5_CONTROL, 0);
206 rdev->irq.hpd[4] = false;
207 break;
208 case RADEON_HPD_6:
209 WREG32(DC_HPD6_CONTROL, 0);
210 rdev->irq.hpd[5] = false;
211 break;
212 default:
213 break;
214 }
215 }
61} 216}
62 217
63void evergreen_hpd_fini(struct radeon_device *rdev) 218void evergreen_bandwidth_update(struct radeon_device *rdev)
64{ 219{
65 /* XXX */ 220 /* XXX */
66} 221}
@@ -83,10 +238,31 @@ static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
83/* 238/*
84 * GART 239 * GART
85 */ 240 */
241void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
242{
243 unsigned i;
244 u32 tmp;
245
246 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
247 for (i = 0; i < rdev->usec_timeout; i++) {
248 /* read MC_STATUS */
249 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
250 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
251 if (tmp == 2) {
252 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
253 return;
254 }
255 if (tmp) {
256 return;
257 }
258 udelay(1);
259 }
260}
261
86int evergreen_pcie_gart_enable(struct radeon_device *rdev) 262int evergreen_pcie_gart_enable(struct radeon_device *rdev)
87{ 263{
88 u32 tmp; 264 u32 tmp;
89 int r, i; 265 int r;
90 266
91 if (rdev->gart.table.vram.robj == NULL) { 267 if (rdev->gart.table.vram.robj == NULL) {
92 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); 268 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
@@ -121,10 +297,9 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
121 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); 297 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
122 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, 298 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
123 (u32)(rdev->dummy_page.addr >> 12)); 299 (u32)(rdev->dummy_page.addr >> 12));
124 for (i = 1; i < 7; i++) 300 WREG32(VM_CONTEXT1_CNTL, 0);
125 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
126 301
127 r600_pcie_gart_tlb_flush(rdev); 302 evergreen_pcie_gart_tlb_flush(rdev);
128 rdev->gart.ready = true; 303 rdev->gart.ready = true;
129 return 0; 304 return 0;
130} 305}
@@ -132,11 +307,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
132void evergreen_pcie_gart_disable(struct radeon_device *rdev) 307void evergreen_pcie_gart_disable(struct radeon_device *rdev)
133{ 308{
134 u32 tmp; 309 u32 tmp;
135 int i, r; 310 int r;
136 311
137 /* Disable all tables */ 312 /* Disable all tables */
138 for (i = 0; i < 7; i++) 313 WREG32(VM_CONTEXT0_CNTL, 0);
139 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 314 WREG32(VM_CONTEXT1_CNTL, 0);
140 315
141 /* Setup L2 cache */ 316 /* Setup L2 cache */
142 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | 317 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
@@ -173,7 +348,6 @@ void evergreen_pcie_gart_fini(struct radeon_device *rdev)
173void evergreen_agp_enable(struct radeon_device *rdev) 348void evergreen_agp_enable(struct radeon_device *rdev)
174{ 349{
175 u32 tmp; 350 u32 tmp;
176 int i;
177 351
178 /* Setup L2 cache */ 352 /* Setup L2 cache */
179 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | 353 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
@@ -193,8 +367,8 @@ void evergreen_agp_enable(struct radeon_device *rdev)
193 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 367 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
194 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 368 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
195 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); 369 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
196 for (i = 0; i < 7; i++) 370 WREG32(VM_CONTEXT0_CNTL, 0);
197 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); 371 WREG32(VM_CONTEXT1_CNTL, 0);
198} 372}
199 373
200static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 374static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -400,40 +574,656 @@ static void evergreen_mc_program(struct radeon_device *rdev)
400 rv515_vga_render_disable(rdev); 574 rv515_vga_render_disable(rdev);
401} 575}
402 576
403#if 0
404/* 577/*
405 * CP. 578 * CP.
406 */ 579 */
407static void evergreen_cp_stop(struct radeon_device *rdev)
408{
409 /* XXX */
410}
411
412 580
413static int evergreen_cp_load_microcode(struct radeon_device *rdev) 581static int evergreen_cp_load_microcode(struct radeon_device *rdev)
414{ 582{
415 /* XXX */ 583 const __be32 *fw_data;
584 int i;
585
586 if (!rdev->me_fw || !rdev->pfp_fw)
587 return -EINVAL;
416 588
589 r700_cp_stop(rdev);
590 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
591
592 fw_data = (const __be32 *)rdev->pfp_fw->data;
593 WREG32(CP_PFP_UCODE_ADDR, 0);
594 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
595 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
596 WREG32(CP_PFP_UCODE_ADDR, 0);
597
598 fw_data = (const __be32 *)rdev->me_fw->data;
599 WREG32(CP_ME_RAM_WADDR, 0);
600 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
601 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
602
603 WREG32(CP_PFP_UCODE_ADDR, 0);
604 WREG32(CP_ME_RAM_WADDR, 0);
605 WREG32(CP_ME_RAM_RADDR, 0);
417 return 0; 606 return 0;
418} 607}
419 608
609int evergreen_cp_resume(struct radeon_device *rdev)
610{
611 u32 tmp;
612 u32 rb_bufsz;
613 int r;
614
615 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
616 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
617 SOFT_RESET_PA |
618 SOFT_RESET_SH |
619 SOFT_RESET_VGT |
620 SOFT_RESET_SX));
621 RREG32(GRBM_SOFT_RESET);
622 mdelay(15);
623 WREG32(GRBM_SOFT_RESET, 0);
624 RREG32(GRBM_SOFT_RESET);
625
626 /* Set ring buffer size */
627 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
628 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
629#ifdef __BIG_ENDIAN
630 tmp |= BUF_SWAP_32BIT;
631#endif
632 WREG32(CP_RB_CNTL, tmp);
633 WREG32(CP_SEM_WAIT_TIMER, 0x4);
634
635 /* Set the write pointer delay */
636 WREG32(CP_RB_WPTR_DELAY, 0);
637
638 /* Initialize the ring buffer's read and write pointers */
639 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
640 WREG32(CP_RB_RPTR_WR, 0);
641 WREG32(CP_RB_WPTR, 0);
642 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
643 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
644 mdelay(1);
645 WREG32(CP_RB_CNTL, tmp);
646
647 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
648 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
649
650 rdev->cp.rptr = RREG32(CP_RB_RPTR);
651 rdev->cp.wptr = RREG32(CP_RB_WPTR);
652
653 r600_cp_start(rdev);
654 rdev->cp.ready = true;
655 r = radeon_ring_test(rdev);
656 if (r) {
657 rdev->cp.ready = false;
658 return r;
659 }
660 return 0;
661}
420 662
421/* 663/*
422 * Core functions 664 * Core functions
423 */ 665 */
424static u32 evergreen_get_tile_pipe_to_backend_map(u32 num_tile_pipes, 666static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
667 u32 num_tile_pipes,
425 u32 num_backends, 668 u32 num_backends,
426 u32 backend_disable_mask) 669 u32 backend_disable_mask)
427{ 670{
428 u32 backend_map = 0; 671 u32 backend_map = 0;
672 u32 enabled_backends_mask = 0;
673 u32 enabled_backends_count = 0;
674 u32 cur_pipe;
675 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
676 u32 cur_backend = 0;
677 u32 i;
678 bool force_no_swizzle;
679
680 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
681 num_tile_pipes = EVERGREEN_MAX_PIPES;
682 if (num_tile_pipes < 1)
683 num_tile_pipes = 1;
684 if (num_backends > EVERGREEN_MAX_BACKENDS)
685 num_backends = EVERGREEN_MAX_BACKENDS;
686 if (num_backends < 1)
687 num_backends = 1;
688
689 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
690 if (((backend_disable_mask >> i) & 1) == 0) {
691 enabled_backends_mask |= (1 << i);
692 ++enabled_backends_count;
693 }
694 if (enabled_backends_count == num_backends)
695 break;
696 }
697
698 if (enabled_backends_count == 0) {
699 enabled_backends_mask = 1;
700 enabled_backends_count = 1;
701 }
702
703 if (enabled_backends_count != num_backends)
704 num_backends = enabled_backends_count;
705
706 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
707 switch (rdev->family) {
708 case CHIP_CEDAR:
709 case CHIP_REDWOOD:
710 force_no_swizzle = false;
711 break;
712 case CHIP_CYPRESS:
713 case CHIP_HEMLOCK:
714 case CHIP_JUNIPER:
715 default:
716 force_no_swizzle = true;
717 break;
718 }
719 if (force_no_swizzle) {
720 bool last_backend_enabled = false;
721
722 force_no_swizzle = false;
723 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
724 if (((enabled_backends_mask >> i) & 1) == 1) {
725 if (last_backend_enabled)
726 force_no_swizzle = true;
727 last_backend_enabled = true;
728 } else
729 last_backend_enabled = false;
730 }
731 }
732
733 switch (num_tile_pipes) {
734 case 1:
735 case 3:
736 case 5:
737 case 7:
738 DRM_ERROR("odd number of pipes!\n");
739 break;
740 case 2:
741 swizzle_pipe[0] = 0;
742 swizzle_pipe[1] = 1;
743 break;
744 case 4:
745 if (force_no_swizzle) {
746 swizzle_pipe[0] = 0;
747 swizzle_pipe[1] = 1;
748 swizzle_pipe[2] = 2;
749 swizzle_pipe[3] = 3;
750 } else {
751 swizzle_pipe[0] = 0;
752 swizzle_pipe[1] = 2;
753 swizzle_pipe[2] = 1;
754 swizzle_pipe[3] = 3;
755 }
756 break;
757 case 6:
758 if (force_no_swizzle) {
759 swizzle_pipe[0] = 0;
760 swizzle_pipe[1] = 1;
761 swizzle_pipe[2] = 2;
762 swizzle_pipe[3] = 3;
763 swizzle_pipe[4] = 4;
764 swizzle_pipe[5] = 5;
765 } else {
766 swizzle_pipe[0] = 0;
767 swizzle_pipe[1] = 2;
768 swizzle_pipe[2] = 4;
769 swizzle_pipe[3] = 1;
770 swizzle_pipe[4] = 3;
771 swizzle_pipe[5] = 5;
772 }
773 break;
774 case 8:
775 if (force_no_swizzle) {
776 swizzle_pipe[0] = 0;
777 swizzle_pipe[1] = 1;
778 swizzle_pipe[2] = 2;
779 swizzle_pipe[3] = 3;
780 swizzle_pipe[4] = 4;
781 swizzle_pipe[5] = 5;
782 swizzle_pipe[6] = 6;
783 swizzle_pipe[7] = 7;
784 } else {
785 swizzle_pipe[0] = 0;
786 swizzle_pipe[1] = 2;
787 swizzle_pipe[2] = 4;
788 swizzle_pipe[3] = 6;
789 swizzle_pipe[4] = 1;
790 swizzle_pipe[5] = 3;
791 swizzle_pipe[6] = 5;
792 swizzle_pipe[7] = 7;
793 }
794 break;
795 }
796
797 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
798 while (((1 << cur_backend) & enabled_backends_mask) == 0)
799 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
800
801 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
802
803 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
804 }
429 805
430 return backend_map; 806 return backend_map;
431} 807}
432#endif
433 808
434static void evergreen_gpu_init(struct radeon_device *rdev) 809static void evergreen_gpu_init(struct radeon_device *rdev)
435{ 810{
436 /* XXX */ 811 u32 cc_rb_backend_disable = 0;
812 u32 cc_gc_shader_pipe_config;
813 u32 gb_addr_config = 0;
814 u32 mc_shared_chmap, mc_arb_ramcfg;
815 u32 gb_backend_map;
816 u32 grbm_gfx_index;
817 u32 sx_debug_1;
818 u32 smx_dc_ctl0;
819 u32 sq_config;
820 u32 sq_lds_resource_mgmt;
821 u32 sq_gpr_resource_mgmt_1;
822 u32 sq_gpr_resource_mgmt_2;
823 u32 sq_gpr_resource_mgmt_3;
824 u32 sq_thread_resource_mgmt;
825 u32 sq_thread_resource_mgmt_2;
826 u32 sq_stack_resource_mgmt_1;
827 u32 sq_stack_resource_mgmt_2;
828 u32 sq_stack_resource_mgmt_3;
829 u32 vgt_cache_invalidation;
830 u32 hdp_host_path_cntl;
831 int i, j, num_shader_engines, ps_thread_count;
832
833 switch (rdev->family) {
834 case CHIP_CYPRESS:
835 case CHIP_HEMLOCK:
836 rdev->config.evergreen.num_ses = 2;
837 rdev->config.evergreen.max_pipes = 4;
838 rdev->config.evergreen.max_tile_pipes = 8;
839 rdev->config.evergreen.max_simds = 10;
840 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
841 rdev->config.evergreen.max_gprs = 256;
842 rdev->config.evergreen.max_threads = 248;
843 rdev->config.evergreen.max_gs_threads = 32;
844 rdev->config.evergreen.max_stack_entries = 512;
845 rdev->config.evergreen.sx_num_of_sets = 4;
846 rdev->config.evergreen.sx_max_export_size = 256;
847 rdev->config.evergreen.sx_max_export_pos_size = 64;
848 rdev->config.evergreen.sx_max_export_smx_size = 192;
849 rdev->config.evergreen.max_hw_contexts = 8;
850 rdev->config.evergreen.sq_num_cf_insts = 2;
851
852 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
853 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
854 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
855 break;
856 case CHIP_JUNIPER:
857 rdev->config.evergreen.num_ses = 1;
858 rdev->config.evergreen.max_pipes = 4;
859 rdev->config.evergreen.max_tile_pipes = 4;
860 rdev->config.evergreen.max_simds = 10;
861 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
862 rdev->config.evergreen.max_gprs = 256;
863 rdev->config.evergreen.max_threads = 248;
864 rdev->config.evergreen.max_gs_threads = 32;
865 rdev->config.evergreen.max_stack_entries = 512;
866 rdev->config.evergreen.sx_num_of_sets = 4;
867 rdev->config.evergreen.sx_max_export_size = 256;
868 rdev->config.evergreen.sx_max_export_pos_size = 64;
869 rdev->config.evergreen.sx_max_export_smx_size = 192;
870 rdev->config.evergreen.max_hw_contexts = 8;
871 rdev->config.evergreen.sq_num_cf_insts = 2;
872
873 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
874 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
875 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
876 break;
877 case CHIP_REDWOOD:
878 rdev->config.evergreen.num_ses = 1;
879 rdev->config.evergreen.max_pipes = 4;
880 rdev->config.evergreen.max_tile_pipes = 4;
881 rdev->config.evergreen.max_simds = 5;
882 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
883 rdev->config.evergreen.max_gprs = 256;
884 rdev->config.evergreen.max_threads = 248;
885 rdev->config.evergreen.max_gs_threads = 32;
886 rdev->config.evergreen.max_stack_entries = 256;
887 rdev->config.evergreen.sx_num_of_sets = 4;
888 rdev->config.evergreen.sx_max_export_size = 256;
889 rdev->config.evergreen.sx_max_export_pos_size = 64;
890 rdev->config.evergreen.sx_max_export_smx_size = 192;
891 rdev->config.evergreen.max_hw_contexts = 8;
892 rdev->config.evergreen.sq_num_cf_insts = 2;
893
894 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
895 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
896 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
897 break;
898 case CHIP_CEDAR:
899 default:
900 rdev->config.evergreen.num_ses = 1;
901 rdev->config.evergreen.max_pipes = 2;
902 rdev->config.evergreen.max_tile_pipes = 2;
903 rdev->config.evergreen.max_simds = 2;
904 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
905 rdev->config.evergreen.max_gprs = 256;
906 rdev->config.evergreen.max_threads = 192;
907 rdev->config.evergreen.max_gs_threads = 16;
908 rdev->config.evergreen.max_stack_entries = 256;
909 rdev->config.evergreen.sx_num_of_sets = 4;
910 rdev->config.evergreen.sx_max_export_size = 128;
911 rdev->config.evergreen.sx_max_export_pos_size = 32;
912 rdev->config.evergreen.sx_max_export_smx_size = 96;
913 rdev->config.evergreen.max_hw_contexts = 4;
914 rdev->config.evergreen.sq_num_cf_insts = 1;
915
916 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
917 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
918 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
919 break;
920 }
921
922 /* Initialize HDP */
923 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
924 WREG32((0x2c14 + j), 0x00000000);
925 WREG32((0x2c18 + j), 0x00000000);
926 WREG32((0x2c1c + j), 0x00000000);
927 WREG32((0x2c20 + j), 0x00000000);
928 WREG32((0x2c24 + j), 0x00000000);
929 }
930
931 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
932
933 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
934
935 cc_gc_shader_pipe_config |=
936 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
937 & EVERGREEN_MAX_PIPES_MASK);
938 cc_gc_shader_pipe_config |=
939 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
940 & EVERGREEN_MAX_SIMDS_MASK);
941
942 cc_rb_backend_disable =
943 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
944 & EVERGREEN_MAX_BACKENDS_MASK);
945
946
947 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
948 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
949
950 switch (rdev->config.evergreen.max_tile_pipes) {
951 case 1:
952 default:
953 gb_addr_config |= NUM_PIPES(0);
954 break;
955 case 2:
956 gb_addr_config |= NUM_PIPES(1);
957 break;
958 case 4:
959 gb_addr_config |= NUM_PIPES(2);
960 break;
961 case 8:
962 gb_addr_config |= NUM_PIPES(3);
963 break;
964 }
965
966 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
967 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
968 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
969 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
970 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
971 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
972
973 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
974 gb_addr_config |= ROW_SIZE(2);
975 else
976 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
977
978 if (rdev->ddev->pdev->device == 0x689e) {
979 u32 efuse_straps_4;
980 u32 efuse_straps_3;
981 u8 efuse_box_bit_131_124;
982
983 WREG32(RCU_IND_INDEX, 0x204);
984 efuse_straps_4 = RREG32(RCU_IND_DATA);
985 WREG32(RCU_IND_INDEX, 0x203);
986 efuse_straps_3 = RREG32(RCU_IND_DATA);
987 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
988
989 switch(efuse_box_bit_131_124) {
990 case 0x00:
991 gb_backend_map = 0x76543210;
992 break;
993 case 0x55:
994 gb_backend_map = 0x77553311;
995 break;
996 case 0x56:
997 gb_backend_map = 0x77553300;
998 break;
999 case 0x59:
1000 gb_backend_map = 0x77552211;
1001 break;
1002 case 0x66:
1003 gb_backend_map = 0x77443300;
1004 break;
1005 case 0x99:
1006 gb_backend_map = 0x66552211;
1007 break;
1008 case 0x5a:
1009 gb_backend_map = 0x77552200;
1010 break;
1011 case 0xaa:
1012 gb_backend_map = 0x66442200;
1013 break;
1014 case 0x95:
1015 gb_backend_map = 0x66553311;
1016 break;
1017 default:
1018 DRM_ERROR("bad backend map, using default\n");
1019 gb_backend_map =
1020 evergreen_get_tile_pipe_to_backend_map(rdev,
1021 rdev->config.evergreen.max_tile_pipes,
1022 rdev->config.evergreen.max_backends,
1023 ((EVERGREEN_MAX_BACKENDS_MASK <<
1024 rdev->config.evergreen.max_backends) &
1025 EVERGREEN_MAX_BACKENDS_MASK));
1026 break;
1027 }
1028 } else if (rdev->ddev->pdev->device == 0x68b9) {
1029 u32 efuse_straps_3;
1030 u8 efuse_box_bit_127_124;
1031
1032 WREG32(RCU_IND_INDEX, 0x203);
1033 efuse_straps_3 = RREG32(RCU_IND_DATA);
1034 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
1035
1036 switch(efuse_box_bit_127_124) {
1037 case 0x0:
1038 gb_backend_map = 0x00003210;
1039 break;
1040 case 0x5:
1041 case 0x6:
1042 case 0x9:
1043 case 0xa:
1044 gb_backend_map = 0x00003311;
1045 break;
1046 default:
1047 DRM_ERROR("bad backend map, using default\n");
1048 gb_backend_map =
1049 evergreen_get_tile_pipe_to_backend_map(rdev,
1050 rdev->config.evergreen.max_tile_pipes,
1051 rdev->config.evergreen.max_backends,
1052 ((EVERGREEN_MAX_BACKENDS_MASK <<
1053 rdev->config.evergreen.max_backends) &
1054 EVERGREEN_MAX_BACKENDS_MASK));
1055 break;
1056 }
1057 } else
1058 gb_backend_map =
1059 evergreen_get_tile_pipe_to_backend_map(rdev,
1060 rdev->config.evergreen.max_tile_pipes,
1061 rdev->config.evergreen.max_backends,
1062 ((EVERGREEN_MAX_BACKENDS_MASK <<
1063 rdev->config.evergreen.max_backends) &
1064 EVERGREEN_MAX_BACKENDS_MASK));
1065
1066 WREG32(GB_BACKEND_MAP, gb_backend_map);
1067 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1068 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1069 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1070
1071 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1072 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1073
1074 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1075 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1076 u32 sp = cc_gc_shader_pipe_config;
1077 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1078
1079 if (i == num_shader_engines) {
1080 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1081 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1082 }
1083
1084 WREG32(GRBM_GFX_INDEX, gfx);
1085 WREG32(RLC_GFX_INDEX, gfx);
1086
1087 WREG32(CC_RB_BACKEND_DISABLE, rb);
1088 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1089 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1090 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1091 }
1092
1093 grbm_gfx_index |= SE_BROADCAST_WRITES;
1094 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1095 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1096
1097 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1098 WREG32(CGTS_TCC_DISABLE, 0);
1099 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1100 WREG32(CGTS_USER_TCC_DISABLE, 0);
1101
1102 /* set HW defaults for 3D engine */
1103 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1104 ROQ_IB2_START(0x2b)));
1105
1106 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1107
1108 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1109 SYNC_GRADIENT |
1110 SYNC_WALKER |
1111 SYNC_ALIGNER));
1112
1113 sx_debug_1 = RREG32(SX_DEBUG_1);
1114 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1115 WREG32(SX_DEBUG_1, sx_debug_1);
1116
1117
1118 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1119 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1120 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1121 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1122
1123 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1124 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1125 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1126
1127 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1128 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1129 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1130
1131 WREG32(VGT_NUM_INSTANCES, 1);
1132 WREG32(SPI_CONFIG_CNTL, 0);
1133 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1134 WREG32(CP_PERFMON_CNTL, 0);
1135
1136 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1137 FETCH_FIFO_HIWATER(0x4) |
1138 DONE_FIFO_HIWATER(0xe0) |
1139 ALU_UPDATE_FIFO_HIWATER(0x8)));
1140
1141 sq_config = RREG32(SQ_CONFIG);
1142 sq_config &= ~(PS_PRIO(3) |
1143 VS_PRIO(3) |
1144 GS_PRIO(3) |
1145 ES_PRIO(3));
1146 sq_config |= (VC_ENABLE |
1147 EXPORT_SRC_C |
1148 PS_PRIO(0) |
1149 VS_PRIO(1) |
1150 GS_PRIO(2) |
1151 ES_PRIO(3));
1152
1153 if (rdev->family == CHIP_CEDAR)
1154 /* no vertex cache */
1155 sq_config &= ~VC_ENABLE;
1156
1157 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1158
1159 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1160 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1161 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1162 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1163 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1164 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1165 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1166
1167 if (rdev->family == CHIP_CEDAR)
1168 ps_thread_count = 96;
1169 else
1170 ps_thread_count = 128;
1171
1172 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1173 sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1174 sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1175 sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1176 sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1177 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1178
1179 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1180 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1181 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1182 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1183 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1184 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1185
1186 WREG32(SQ_CONFIG, sq_config);
1187 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1188 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1189 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1190 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1191 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1192 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1193 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1194 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1195 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1196 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1197
1198 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1199 FORCE_EOV_MAX_REZ_CNT(255)));
1200
1201 if (rdev->family == CHIP_CEDAR)
1202 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1203 else
1204 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1205 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1206 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1207
1208 WREG32(VGT_GS_VERTEX_REUSE, 16);
1209 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1210
1211 WREG32(CB_PERF_CTR0_SEL_0, 0);
1212 WREG32(CB_PERF_CTR0_SEL_1, 0);
1213 WREG32(CB_PERF_CTR1_SEL_0, 0);
1214 WREG32(CB_PERF_CTR1_SEL_1, 0);
1215 WREG32(CB_PERF_CTR2_SEL_0, 0);
1216 WREG32(CB_PERF_CTR2_SEL_1, 0);
1217 WREG32(CB_PERF_CTR3_SEL_0, 0);
1218 WREG32(CB_PERF_CTR3_SEL_1, 0);
1219
1220 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1221 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1222
1223 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1224
1225 udelay(50);
1226
437} 1227}
438 1228
439int evergreen_mc_init(struct radeon_device *rdev) 1229int evergreen_mc_init(struct radeon_device *rdev)
@@ -493,15 +1283,604 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
493 return false; 1283 return false;
494} 1284}
495 1285
1286static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1287{
1288 struct evergreen_mc_save save;
1289 u32 srbm_reset = 0;
1290 u32 grbm_reset = 0;
1291
1292 dev_info(rdev->dev, "GPU softreset \n");
1293 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1294 RREG32(GRBM_STATUS));
1295 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1296 RREG32(GRBM_STATUS_SE0));
1297 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1298 RREG32(GRBM_STATUS_SE1));
1299 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1300 RREG32(SRBM_STATUS));
1301 evergreen_mc_stop(rdev, &save);
1302 if (evergreen_mc_wait_for_idle(rdev)) {
1303 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1304 }
1305 /* Disable CP parsing/prefetching */
1306 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1307
1308 /* reset all the gfx blocks */
1309 grbm_reset = (SOFT_RESET_CP |
1310 SOFT_RESET_CB |
1311 SOFT_RESET_DB |
1312 SOFT_RESET_PA |
1313 SOFT_RESET_SC |
1314 SOFT_RESET_SPI |
1315 SOFT_RESET_SH |
1316 SOFT_RESET_SX |
1317 SOFT_RESET_TC |
1318 SOFT_RESET_TA |
1319 SOFT_RESET_VC |
1320 SOFT_RESET_VGT);
1321
1322 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1323 WREG32(GRBM_SOFT_RESET, grbm_reset);
1324 (void)RREG32(GRBM_SOFT_RESET);
1325 udelay(50);
1326 WREG32(GRBM_SOFT_RESET, 0);
1327 (void)RREG32(GRBM_SOFT_RESET);
1328
1329 /* reset all the system blocks */
1330 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1331
1332 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1333 WREG32(SRBM_SOFT_RESET, srbm_reset);
1334 (void)RREG32(SRBM_SOFT_RESET);
1335 udelay(50);
1336 WREG32(SRBM_SOFT_RESET, 0);
1337 (void)RREG32(SRBM_SOFT_RESET);
1338 /* Wait a little for things to settle down */
1339 udelay(50);
1340 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
1341 RREG32(GRBM_STATUS));
1342 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
1343 RREG32(GRBM_STATUS_SE0));
1344 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
1345 RREG32(GRBM_STATUS_SE1));
1346 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
1347 RREG32(SRBM_STATUS));
1348 /* After reset we need to reinit the asic as GPU often endup in an
1349 * incoherent state.
1350 */
1351 atom_asic_init(rdev->mode_info.atom_context);
1352 evergreen_mc_resume(rdev, &save);
1353 return 0;
1354}
1355
496int evergreen_asic_reset(struct radeon_device *rdev) 1356int evergreen_asic_reset(struct radeon_device *rdev)
497{ 1357{
498 /* FIXME: implement for evergreen */ 1358 return evergreen_gpu_soft_reset(rdev);
1359}
1360
1361/* Interrupts */
1362
1363u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1364{
1365 switch (crtc) {
1366 case 0:
1367 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1368 case 1:
1369 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1370 case 2:
1371 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1372 case 3:
1373 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1374 case 4:
1375 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1376 case 5:
1377 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1378 default:
1379 return 0;
1380 }
1381}
1382
1383void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1384{
1385 u32 tmp;
1386
1387 WREG32(CP_INT_CNTL, 0);
1388 WREG32(GRBM_INT_CNTL, 0);
1389 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1390 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1391 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1392 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1393 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1394 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1395
1396 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1397 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1398 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1399 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1400 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1401 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1402
1403 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1404 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1405
1406 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1407 WREG32(DC_HPD1_INT_CONTROL, tmp);
1408 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1409 WREG32(DC_HPD2_INT_CONTROL, tmp);
1410 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1411 WREG32(DC_HPD3_INT_CONTROL, tmp);
1412 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1413 WREG32(DC_HPD4_INT_CONTROL, tmp);
1414 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1415 WREG32(DC_HPD5_INT_CONTROL, tmp);
1416 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1417 WREG32(DC_HPD6_INT_CONTROL, tmp);
1418
1419}
1420
1421int evergreen_irq_set(struct radeon_device *rdev)
1422{
1423 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1424 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1425 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
1426
1427 if (!rdev->irq.installed) {
1428 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1429 return -EINVAL;
1430 }
1431 /* don't enable anything if the ih is disabled */
1432 if (!rdev->ih.enabled) {
1433 r600_disable_interrupts(rdev);
1434 /* force the active interrupt state to all disabled */
1435 evergreen_disable_interrupt_state(rdev);
1436 return 0;
1437 }
1438
1439 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1440 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1441 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1442 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1443 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1444 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1445
1446 if (rdev->irq.sw_int) {
1447 DRM_DEBUG("evergreen_irq_set: sw int\n");
1448 cp_int_cntl |= RB_INT_ENABLE;
1449 }
1450 if (rdev->irq.crtc_vblank_int[0]) {
1451 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1452 crtc1 |= VBLANK_INT_MASK;
1453 }
1454 if (rdev->irq.crtc_vblank_int[1]) {
1455 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1456 crtc2 |= VBLANK_INT_MASK;
1457 }
1458 if (rdev->irq.crtc_vblank_int[2]) {
1459 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1460 crtc3 |= VBLANK_INT_MASK;
1461 }
1462 if (rdev->irq.crtc_vblank_int[3]) {
1463 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1464 crtc4 |= VBLANK_INT_MASK;
1465 }
1466 if (rdev->irq.crtc_vblank_int[4]) {
1467 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1468 crtc5 |= VBLANK_INT_MASK;
1469 }
1470 if (rdev->irq.crtc_vblank_int[5]) {
1471 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1472 crtc6 |= VBLANK_INT_MASK;
1473 }
1474 if (rdev->irq.hpd[0]) {
1475 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1476 hpd1 |= DC_HPDx_INT_EN;
1477 }
1478 if (rdev->irq.hpd[1]) {
1479 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1480 hpd2 |= DC_HPDx_INT_EN;
1481 }
1482 if (rdev->irq.hpd[2]) {
1483 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1484 hpd3 |= DC_HPDx_INT_EN;
1485 }
1486 if (rdev->irq.hpd[3]) {
1487 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1488 hpd4 |= DC_HPDx_INT_EN;
1489 }
1490 if (rdev->irq.hpd[4]) {
1491 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1492 hpd5 |= DC_HPDx_INT_EN;
1493 }
1494 if (rdev->irq.hpd[5]) {
1495 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1496 hpd6 |= DC_HPDx_INT_EN;
1497 }
1498
1499 WREG32(CP_INT_CNTL, cp_int_cntl);
1500
1501 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1502 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1503 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1504 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1505 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1506 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1507
1508 WREG32(DC_HPD1_INT_CONTROL, hpd1);
1509 WREG32(DC_HPD2_INT_CONTROL, hpd2);
1510 WREG32(DC_HPD3_INT_CONTROL, hpd3);
1511 WREG32(DC_HPD4_INT_CONTROL, hpd4);
1512 WREG32(DC_HPD5_INT_CONTROL, hpd5);
1513 WREG32(DC_HPD6_INT_CONTROL, hpd6);
1514
499 return 0; 1515 return 0;
500} 1516}
501 1517
1518static inline void evergreen_irq_ack(struct radeon_device *rdev,
1519 u32 *disp_int,
1520 u32 *disp_int_cont,
1521 u32 *disp_int_cont2,
1522 u32 *disp_int_cont3,
1523 u32 *disp_int_cont4,
1524 u32 *disp_int_cont5)
1525{
1526 u32 tmp;
1527
1528 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1529 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1530 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1531 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1532 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1533 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1534
1535 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1536 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1537 if (*disp_int & LB_D1_VLINE_INTERRUPT)
1538 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1539
1540 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1541 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1542 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1543 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1544
1545 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1546 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1547 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1548 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1549
1550 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1551 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1552 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1553 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1554
1555 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1556 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1557 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1558 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1559
1560 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1561 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1562 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1563 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1564
1565 if (*disp_int & DC_HPD1_INTERRUPT) {
1566 tmp = RREG32(DC_HPD1_INT_CONTROL);
1567 tmp |= DC_HPDx_INT_ACK;
1568 WREG32(DC_HPD1_INT_CONTROL, tmp);
1569 }
1570 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1571 tmp = RREG32(DC_HPD2_INT_CONTROL);
1572 tmp |= DC_HPDx_INT_ACK;
1573 WREG32(DC_HPD2_INT_CONTROL, tmp);
1574 }
1575 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1576 tmp = RREG32(DC_HPD3_INT_CONTROL);
1577 tmp |= DC_HPDx_INT_ACK;
1578 WREG32(DC_HPD3_INT_CONTROL, tmp);
1579 }
1580 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1581 tmp = RREG32(DC_HPD4_INT_CONTROL);
1582 tmp |= DC_HPDx_INT_ACK;
1583 WREG32(DC_HPD4_INT_CONTROL, tmp);
1584 }
1585 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1586 tmp = RREG32(DC_HPD5_INT_CONTROL);
1587 tmp |= DC_HPDx_INT_ACK;
1588 WREG32(DC_HPD5_INT_CONTROL, tmp);
1589 }
1590 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1591 tmp = RREG32(DC_HPD5_INT_CONTROL);
1592 tmp |= DC_HPDx_INT_ACK;
1593 WREG32(DC_HPD6_INT_CONTROL, tmp);
1594 }
1595}
1596
1597void evergreen_irq_disable(struct radeon_device *rdev)
1598{
1599 u32 disp_int, disp_int_cont, disp_int_cont2;
1600 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1601
1602 r600_disable_interrupts(rdev);
1603 /* Wait and acknowledge irq */
1604 mdelay(1);
1605 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1606 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1607 evergreen_disable_interrupt_state(rdev);
1608}
1609
1610static void evergreen_irq_suspend(struct radeon_device *rdev)
1611{
1612 evergreen_irq_disable(rdev);
1613 r600_rlc_stop(rdev);
1614}
1615
1616static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1617{
1618 u32 wptr, tmp;
1619
1620 /* XXX use writeback */
1621 wptr = RREG32(IH_RB_WPTR);
1622
1623 if (wptr & RB_OVERFLOW) {
1624 /* When a ring buffer overflow happen start parsing interrupt
1625 * from the last not overwritten vector (wptr + 16). Hopefully
1626 * this should allow us to catchup.
1627 */
1628 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1629 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1630 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1631 tmp = RREG32(IH_RB_CNTL);
1632 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1633 WREG32(IH_RB_CNTL, tmp);
1634 }
1635 return (wptr & rdev->ih.ptr_mask);
1636}
1637
1638int evergreen_irq_process(struct radeon_device *rdev)
1639{
1640 u32 wptr = evergreen_get_ih_wptr(rdev);
1641 u32 rptr = rdev->ih.rptr;
1642 u32 src_id, src_data;
1643 u32 ring_index;
1644 u32 disp_int, disp_int_cont, disp_int_cont2;
1645 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1646 unsigned long flags;
1647 bool queue_hotplug = false;
1648
1649 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1650 if (!rdev->ih.enabled)
1651 return IRQ_NONE;
1652
1653 spin_lock_irqsave(&rdev->ih.lock, flags);
1654
1655 if (rptr == wptr) {
1656 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1657 return IRQ_NONE;
1658 }
1659 if (rdev->shutdown) {
1660 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1661 return IRQ_NONE;
1662 }
1663
1664restart_ih:
1665 /* display interrupts */
1666 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1667 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1668
1669 rdev->ih.wptr = wptr;
1670 while (rptr != wptr) {
1671 /* wptr/rptr are in bytes! */
1672 ring_index = rptr / 4;
1673 src_id = rdev->ih.ring[ring_index] & 0xff;
1674 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1675
1676 switch (src_id) {
1677 case 1: /* D1 vblank/vline */
1678 switch (src_data) {
1679 case 0: /* D1 vblank */
1680 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1681 drm_handle_vblank(rdev->ddev, 0);
1682 wake_up(&rdev->irq.vblank_queue);
1683 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1684 DRM_DEBUG("IH: D1 vblank\n");
1685 }
1686 break;
1687 case 1: /* D1 vline */
1688 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1689 disp_int &= ~LB_D1_VLINE_INTERRUPT;
1690 DRM_DEBUG("IH: D1 vline\n");
1691 }
1692 break;
1693 default:
1694 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1695 break;
1696 }
1697 break;
1698 case 2: /* D2 vblank/vline */
1699 switch (src_data) {
1700 case 0: /* D2 vblank */
1701 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1702 drm_handle_vblank(rdev->ddev, 1);
1703 wake_up(&rdev->irq.vblank_queue);
1704 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1705 DRM_DEBUG("IH: D2 vblank\n");
1706 }
1707 break;
1708 case 1: /* D2 vline */
1709 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1710 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1711 DRM_DEBUG("IH: D2 vline\n");
1712 }
1713 break;
1714 default:
1715 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1716 break;
1717 }
1718 break;
1719 case 3: /* D3 vblank/vline */
1720 switch (src_data) {
1721 case 0: /* D3 vblank */
1722 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1723 drm_handle_vblank(rdev->ddev, 2);
1724 wake_up(&rdev->irq.vblank_queue);
1725 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1726 DRM_DEBUG("IH: D3 vblank\n");
1727 }
1728 break;
1729 case 1: /* D3 vline */
1730 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1731 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1732 DRM_DEBUG("IH: D3 vline\n");
1733 }
1734 break;
1735 default:
1736 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1737 break;
1738 }
1739 break;
1740 case 4: /* D4 vblank/vline */
1741 switch (src_data) {
1742 case 0: /* D4 vblank */
1743 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1744 drm_handle_vblank(rdev->ddev, 3);
1745 wake_up(&rdev->irq.vblank_queue);
1746 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1747 DRM_DEBUG("IH: D4 vblank\n");
1748 }
1749 break;
1750 case 1: /* D4 vline */
1751 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1752 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1753 DRM_DEBUG("IH: D4 vline\n");
1754 }
1755 break;
1756 default:
1757 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1758 break;
1759 }
1760 break;
1761 case 5: /* D5 vblank/vline */
1762 switch (src_data) {
1763 case 0: /* D5 vblank */
1764 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1765 drm_handle_vblank(rdev->ddev, 4);
1766 wake_up(&rdev->irq.vblank_queue);
1767 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1768 DRM_DEBUG("IH: D5 vblank\n");
1769 }
1770 break;
1771 case 1: /* D5 vline */
1772 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1773 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1774 DRM_DEBUG("IH: D5 vline\n");
1775 }
1776 break;
1777 default:
1778 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1779 break;
1780 }
1781 break;
1782 case 6: /* D6 vblank/vline */
1783 switch (src_data) {
1784 case 0: /* D6 vblank */
1785 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1786 drm_handle_vblank(rdev->ddev, 5);
1787 wake_up(&rdev->irq.vblank_queue);
1788 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1789 DRM_DEBUG("IH: D6 vblank\n");
1790 }
1791 break;
1792 case 1: /* D6 vline */
1793 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1794 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1795 DRM_DEBUG("IH: D6 vline\n");
1796 }
1797 break;
1798 default:
1799 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1800 break;
1801 }
1802 break;
1803 case 42: /* HPD hotplug */
1804 switch (src_data) {
1805 case 0:
1806 if (disp_int & DC_HPD1_INTERRUPT) {
1807 disp_int &= ~DC_HPD1_INTERRUPT;
1808 queue_hotplug = true;
1809 DRM_DEBUG("IH: HPD1\n");
1810 }
1811 break;
1812 case 1:
1813 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1814 disp_int_cont &= ~DC_HPD2_INTERRUPT;
1815 queue_hotplug = true;
1816 DRM_DEBUG("IH: HPD2\n");
1817 }
1818 break;
1819 case 2:
1820 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1821 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1822 queue_hotplug = true;
1823 DRM_DEBUG("IH: HPD3\n");
1824 }
1825 break;
1826 case 3:
1827 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1828 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1829 queue_hotplug = true;
1830 DRM_DEBUG("IH: HPD4\n");
1831 }
1832 break;
1833 case 4:
1834 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1835 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1836 queue_hotplug = true;
1837 DRM_DEBUG("IH: HPD5\n");
1838 }
1839 break;
1840 case 5:
1841 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1842 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1843 queue_hotplug = true;
1844 DRM_DEBUG("IH: HPD6\n");
1845 }
1846 break;
1847 default:
1848 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1849 break;
1850 }
1851 break;
1852 case 176: /* CP_INT in ring buffer */
1853 case 177: /* CP_INT in IB1 */
1854 case 178: /* CP_INT in IB2 */
1855 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
1856 radeon_fence_process(rdev);
1857 break;
1858 case 181: /* CP EOP event */
1859 DRM_DEBUG("IH: CP EOP\n");
1860 break;
1861 default:
1862 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1863 break;
1864 }
1865
1866 /* wptr/rptr are in bytes! */
1867 rptr += 16;
1868 rptr &= rdev->ih.ptr_mask;
1869 }
1870 /* make sure wptr hasn't changed while processing */
1871 wptr = evergreen_get_ih_wptr(rdev);
1872 if (wptr != rdev->ih.wptr)
1873 goto restart_ih;
1874 if (queue_hotplug)
1875 queue_work(rdev->wq, &rdev->hotplug_work);
1876 rdev->ih.rptr = rptr;
1877 WREG32(IH_RB_RPTR, rdev->ih.rptr);
1878 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1879 return IRQ_HANDLED;
1880}
1881
502static int evergreen_startup(struct radeon_device *rdev) 1882static int evergreen_startup(struct radeon_device *rdev)
503{ 1883{
504#if 0
505 int r; 1884 int r;
506 1885
507 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 1886 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
@@ -511,17 +1890,15 @@ static int evergreen_startup(struct radeon_device *rdev)
511 return r; 1890 return r;
512 } 1891 }
513 } 1892 }
514#endif 1893
515 evergreen_mc_program(rdev); 1894 evergreen_mc_program(rdev);
516#if 0
517 if (rdev->flags & RADEON_IS_AGP) { 1895 if (rdev->flags & RADEON_IS_AGP) {
518 evergreem_agp_enable(rdev); 1896 evergreen_agp_enable(rdev);
519 } else { 1897 } else {
520 r = evergreen_pcie_gart_enable(rdev); 1898 r = evergreen_pcie_gart_enable(rdev);
521 if (r) 1899 if (r)
522 return r; 1900 return r;
523 } 1901 }
524#endif
525 evergreen_gpu_init(rdev); 1902 evergreen_gpu_init(rdev);
526#if 0 1903#if 0
527 if (!rdev->r600_blit.shader_obj) { 1904 if (!rdev->r600_blit.shader_obj) {
@@ -542,6 +1919,7 @@ static int evergreen_startup(struct radeon_device *rdev)
542 DRM_ERROR("failed to pin blit object %d\n", r); 1919 DRM_ERROR("failed to pin blit object %d\n", r);
543 return r; 1920 return r;
544 } 1921 }
1922#endif
545 1923
546 /* Enable IRQ */ 1924 /* Enable IRQ */
547 r = r600_irq_init(rdev); 1925 r = r600_irq_init(rdev);
@@ -550,7 +1928,7 @@ static int evergreen_startup(struct radeon_device *rdev)
550 radeon_irq_kms_fini(rdev); 1928 radeon_irq_kms_fini(rdev);
551 return r; 1929 return r;
552 } 1930 }
553 r600_irq_set(rdev); 1931 evergreen_irq_set(rdev);
554 1932
555 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1933 r = radeon_ring_init(rdev, rdev->cp.ring_size);
556 if (r) 1934 if (r)
@@ -558,12 +1936,12 @@ static int evergreen_startup(struct radeon_device *rdev)
558 r = evergreen_cp_load_microcode(rdev); 1936 r = evergreen_cp_load_microcode(rdev);
559 if (r) 1937 if (r)
560 return r; 1938 return r;
561 r = r600_cp_resume(rdev); 1939 r = evergreen_cp_resume(rdev);
562 if (r) 1940 if (r)
563 return r; 1941 return r;
564 /* write back buffer are not vital so don't worry about failure */ 1942 /* write back buffer are not vital so don't worry about failure */
565 r600_wb_enable(rdev); 1943 r600_wb_enable(rdev);
566#endif 1944
567 return 0; 1945 return 0;
568} 1946}
569 1947
@@ -588,13 +1966,13 @@ int evergreen_resume(struct radeon_device *rdev)
588 DRM_ERROR("r600 startup failed on resume\n"); 1966 DRM_ERROR("r600 startup failed on resume\n");
589 return r; 1967 return r;
590 } 1968 }
591#if 0 1969
592 r = r600_ib_test(rdev); 1970 r = r600_ib_test(rdev);
593 if (r) { 1971 if (r) {
594 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1972 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
595 return r; 1973 return r;
596 } 1974 }
597#endif 1975
598 return r; 1976 return r;
599 1977
600} 1978}
@@ -603,12 +1981,14 @@ int evergreen_suspend(struct radeon_device *rdev)
603{ 1981{
604#if 0 1982#if 0
605 int r; 1983 int r;
606 1984#endif
607 /* FIXME: we should wait for ring to be empty */ 1985 /* FIXME: we should wait for ring to be empty */
608 r700_cp_stop(rdev); 1986 r700_cp_stop(rdev);
609 rdev->cp.ready = false; 1987 rdev->cp.ready = false;
1988 evergreen_irq_suspend(rdev);
610 r600_wb_disable(rdev); 1989 r600_wb_disable(rdev);
611 evergreen_pcie_gart_disable(rdev); 1990 evergreen_pcie_gart_disable(rdev);
1991#if 0
612 /* unpin shaders bo */ 1992 /* unpin shaders bo */
613 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1993 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
614 if (likely(r == 0)) { 1994 if (likely(r == 0)) {
@@ -708,7 +2088,7 @@ int evergreen_init(struct radeon_device *rdev)
708 r = radeon_bo_init(rdev); 2088 r = radeon_bo_init(rdev);
709 if (r) 2089 if (r)
710 return r; 2090 return r;
711#if 0 2091
712 r = radeon_irq_kms_init(rdev); 2092 r = radeon_irq_kms_init(rdev);
713 if (r) 2093 if (r)
714 return r; 2094 return r;
@@ -722,14 +2102,16 @@ int evergreen_init(struct radeon_device *rdev)
722 r = r600_pcie_gart_init(rdev); 2102 r = r600_pcie_gart_init(rdev);
723 if (r) 2103 if (r)
724 return r; 2104 return r;
725#endif 2105
726 rdev->accel_working = false; 2106 rdev->accel_working = false;
727 r = evergreen_startup(rdev); 2107 r = evergreen_startup(rdev);
728 if (r) { 2108 if (r) {
729 evergreen_suspend(rdev); 2109 dev_err(rdev->dev, "disabling GPU acceleration\n");
730 /*r600_wb_fini(rdev);*/ 2110 r700_cp_fini(rdev);
731 /*radeon_ring_fini(rdev);*/ 2111 r600_wb_fini(rdev);
732 /*evergreen_pcie_gart_fini(rdev);*/ 2112 r600_irq_fini(rdev);
2113 radeon_irq_kms_fini(rdev);
2114 evergreen_pcie_gart_fini(rdev);
733 rdev->accel_working = false; 2115 rdev->accel_working = false;
734 } 2116 }
735 if (rdev->accel_working) { 2117 if (rdev->accel_working) {
@@ -750,15 +2132,12 @@ int evergreen_init(struct radeon_device *rdev)
750void evergreen_fini(struct radeon_device *rdev) 2132void evergreen_fini(struct radeon_device *rdev)
751{ 2133{
752 radeon_pm_fini(rdev); 2134 radeon_pm_fini(rdev);
753 evergreen_suspend(rdev); 2135 /*r600_blit_fini(rdev);*/
754#if 0 2136 r700_cp_fini(rdev);
755 r600_blit_fini(rdev); 2137 r600_wb_fini(rdev);
756 r600_irq_fini(rdev); 2138 r600_irq_fini(rdev);
757 radeon_irq_kms_fini(rdev); 2139 radeon_irq_kms_fini(rdev);
758 radeon_ring_fini(rdev);
759 r600_wb_fini(rdev);
760 evergreen_pcie_gart_fini(rdev); 2140 evergreen_pcie_gart_fini(rdev);
761#endif
762 radeon_gem_fini(rdev); 2141 radeon_gem_fini(rdev);
763 radeon_fence_driver_fini(rdev); 2142 radeon_fence_driver_fini(rdev);
764 radeon_clocks_fini(rdev); 2143 radeon_clocks_fini(rdev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-22 21:08:01 -0500