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authorAlex Deucher <alexdeucher@gmail.com>2010-04-22 12:52:11 -0400
committerDave Airlie <airlied@redhat.com>2010-05-18 04:20:49 -0400
commit2031f77ca9c17133869b265210418959a909d259 (patch)
tree21fc2aedea8f3c80c4de1d7b1168479bc7a1ce98 /drivers/gpu/drm/radeon/evergreen.c
parentdef9ba9cf6a8266ee1ffd72556db002c3a2663db (diff)
drm/radeon/kms: add support for gui idle interrupts (v4)
Useful for certain power management operations. You need to wait for the GUI engine (2D, 3D, CP, etc.) to be idle before changing clocks or adjusting engine parameters. (v2) Fix gui idle enable on pre-r6xx asics (v3) The gui idle interrrupt status bit is permanently asserted on pre-r6xx chips, but the interrrupt is still generated. workaround it in the driver. (v4) Add support for evergreen Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index b3d168fb89e5..0137a4cd90f5 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1418,6 +1418,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
1418 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; 1418 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1419 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 1419 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1420 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 1420 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
1421 u32 grbm_int_cntl = 0;
1421 1422
1422 if (!rdev->irq.installed) { 1423 if (!rdev->irq.installed) {
1423 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n"); 1424 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
@@ -1490,8 +1491,13 @@ int evergreen_irq_set(struct radeon_device *rdev)
1490 DRM_DEBUG("evergreen_irq_set: hpd 6\n"); 1491 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1491 hpd6 |= DC_HPDx_INT_EN; 1492 hpd6 |= DC_HPDx_INT_EN;
1492 } 1493 }
1494 if (rdev->irq.gui_idle) {
1495 DRM_DEBUG("gui idle\n");
1496 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
1497 }
1493 1498
1494 WREG32(CP_INT_CNTL, cp_int_cntl); 1499 WREG32(CP_INT_CNTL, cp_int_cntl);
1500 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
1495 1501
1496 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 1502 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1497 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 1503 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
@@ -1853,6 +1859,11 @@ restart_ih:
1853 case 181: /* CP EOP event */ 1859 case 181: /* CP EOP event */
1854 DRM_DEBUG("IH: CP EOP\n"); 1860 DRM_DEBUG("IH: CP EOP\n");
1855 break; 1861 break;
1862 case 233: /* GUI IDLE */
1863 DRM_DEBUG("IH: CP EOP\n");
1864 rdev->pm.gui_idle = true;
1865 wake_up(&rdev->irq.idle_queue);
1866 break;
1856 default: 1867 default:
1857 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data); 1868 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1858 break; 1869 break;