drm/radeon: fix multi-head power profile stability on BTC+ asics

vddci needs to track mclk for multi-head.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

1 files changed, 13 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 2916de896a60..3c38ea46531c 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -403,6 +403,19 @@ void evergreen_pm_misc(struct radeon_device *rdev)
                         rdev->pm.current_vddc = voltage->voltage;
                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
                 }
+
+                /* starting with BTC, there is one state that is used for both
+                 * MH and SH.  Difference is that we always use the high clock index for
+                 * mclk and vddci.
+                 */
+                if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
+                    (rdev->family >= CHIP_BARTS) &&
+                    rdev->pm.active_crtc_count &&
+                    ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
+                     (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
+                        voltage = &rdev->pm.power_state[req_ps_idx].
+                                clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage;
+
                 /* 0xff01 is a flag rather then an actual voltage */
                 if (voltage->vddci == 0xff01)
                         return;