drm/radeon: reset dma engine on gpu reset (v2)

This try to reset the dma engine when performing gpu reset. Hopefully
bringing back the gpu dma engine in sane state.

v2: agd5f: fix dma reset on cayman/TN, add support for SI

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 21 insertions, 9 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 6dc9ee78f4a8..f92f6bb18872 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2309,19 +2309,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *rin
 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
 {
         struct evergreen_mc_save save;
-        u32 grbm_reset = 0;
+        u32 grbm_reset = 0, tmp;
 
         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
                 return 0;
 
         dev_info(rdev->dev, "GPU softreset \n");
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));
@@ -2337,9 +2337,21 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
         if (evergreen_mc_wait_for_idle(rdev)) {
                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
         }
+
         /* Disable CP parsing/prefetching */
         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
 
+        /* Disable DMA */
+        tmp = RREG32(DMA_RB_CNTL);
+        tmp &= ~DMA_RB_ENABLE;
+        WREG32(DMA_RB_CNTL, tmp);
+
+        /* Reset dma */
+        WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
+        RREG32(SRBM_SOFT_RESET);
+        udelay(50);
+        WREG32(SRBM_SOFT_RESET, 0);
+
         /* reset all the gfx blocks */
         grbm_reset = (SOFT_RESET_CP |
                       SOFT_RESET_CB |
@@ -2362,13 +2374,13 @@ static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
         (void)RREG32(GRBM_SOFT_RESET);
         /* Wait a little for things to settle down */
         udelay(50);
-        dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
                 RREG32(GRBM_STATUS));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE0));
-        dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
+        dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
                 RREG32(GRBM_STATUS_SE1));
-        dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
+        dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
                 RREG32(SRBM_STATUS));
         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
                 RREG32(CP_STALLED_STAT1));