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author | Alex Deucher <alexander.deucher@amd.com> | 2012-08-15 17:13:53 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2012-09-20 13:10:32 -0400 |
commit | 4a15903db02026728d0cf2755c6fabae16b8db6a (patch) | |
tree | ba2dabd444e9cca0c496f1a777dfc52948ceaaf7 /drivers/gpu/drm/radeon/evergreen.c | |
parent | 16c58081eb95e35f284421176f355eccfc773bbe (diff) |
drm/radeon/dce4+: don't use radeon_crtc for vblank callback
This might be called before we've allocated the radeon_crtcs
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index e93b80a6d4e9..0c79d9eb2ce4 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -37,6 +37,16 @@ | |||
37 | #define EVERGREEN_PFP_UCODE_SIZE 1120 | 37 | #define EVERGREEN_PFP_UCODE_SIZE 1120 |
38 | #define EVERGREEN_PM4_UCODE_SIZE 1376 | 38 | #define EVERGREEN_PM4_UCODE_SIZE 1376 |
39 | 39 | ||
40 | static const u32 crtc_offsets[6] = | ||
41 | { | ||
42 | EVERGREEN_CRTC0_REGISTER_OFFSET, | ||
43 | EVERGREEN_CRTC1_REGISTER_OFFSET, | ||
44 | EVERGREEN_CRTC2_REGISTER_OFFSET, | ||
45 | EVERGREEN_CRTC3_REGISTER_OFFSET, | ||
46 | EVERGREEN_CRTC4_REGISTER_OFFSET, | ||
47 | EVERGREEN_CRTC5_REGISTER_OFFSET | ||
48 | }; | ||
49 | |||
40 | static void evergreen_gpu_init(struct radeon_device *rdev); | 50 | static void evergreen_gpu_init(struct radeon_device *rdev); |
41 | void evergreen_fini(struct radeon_device *rdev); | 51 | void evergreen_fini(struct radeon_device *rdev); |
42 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev); | 52 | void evergreen_pcie_gen2_enable(struct radeon_device *rdev); |
@@ -109,17 +119,19 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) | |||
109 | */ | 119 | */ |
110 | void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) | 120 | void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) |
111 | { | 121 | { |
112 | struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc]; | ||
113 | int i; | 122 | int i; |
114 | 123 | ||
115 | if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) { | 124 | if (crtc >= rdev->num_crtc) |
125 | return; | ||
126 | |||
127 | if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) { | ||
116 | for (i = 0; i < rdev->usec_timeout; i++) { | 128 | for (i = 0; i < rdev->usec_timeout; i++) { |
117 | if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)) | 129 | if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)) |
118 | break; | 130 | break; |
119 | udelay(1); | 131 | udelay(1); |
120 | } | 132 | } |
121 | for (i = 0; i < rdev->usec_timeout; i++) { | 133 | for (i = 0; i < rdev->usec_timeout; i++) { |
122 | if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK) | 134 | if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) |
123 | break; | 135 | break; |
124 | udelay(1); | 136 | udelay(1); |
125 | } | 137 | } |