drm/radeon: properly program gart on rv740, juniper, cypress, barts, hemlock

Need to program an additional VM register.  This doesn't not currently
cause any problems, but allows us to program the proper backend
map in a subsequent patch which should improve performance on these
asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 5 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 5d9c2c64a8e2..0408ac27a863 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1029,6 +1029,11 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
+                if ((rdev->family == CHIP_JUNIPER) ||
+                    (rdev->family == CHIP_CYPRESS) ||
+                    (rdev->family == CHIP_HEMLOCK) ||
+                    (rdev->family == CHIP_BARTS))
+                        WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
         }
         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);