diff options
author | Alex Deucher <alexander.deucher@amd.com> | 2014-06-02 16:13:21 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2014-06-09 22:06:55 -0400 |
commit | 65fcf668ee7f2de2fbd580e1297336045f1ef6f4 (patch) | |
tree | 17064a99c2cf9b0e6d4baab83e654758edef4617 /drivers/gpu/drm/radeon/cik.c | |
parent | 478b6e72721807953bc3513fc5895d5f007614e3 (diff) |
drm/radeon: add query for number of active CUs
Query to find out how many compute units on a GPU.
Useful for OpenCL usermode drivers.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r-- | drivers/gpu/drm/radeon/cik.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index e4b2f2b51bb8..dcd4518a9b08 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c | |||
@@ -80,6 +80,7 @@ extern int sumo_rlc_init(struct radeon_device *rdev); | |||
80 | extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); | 80 | extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
81 | extern void si_rlc_reset(struct radeon_device *rdev); | 81 | extern void si_rlc_reset(struct radeon_device *rdev); |
82 | extern void si_init_uvd_internal_cg(struct radeon_device *rdev); | 82 | extern void si_init_uvd_internal_cg(struct radeon_device *rdev); |
83 | static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh); | ||
83 | extern int cik_sdma_resume(struct radeon_device *rdev); | 84 | extern int cik_sdma_resume(struct radeon_device *rdev); |
84 | extern void cik_sdma_enable(struct radeon_device *rdev, bool enable); | 85 | extern void cik_sdma_enable(struct radeon_device *rdev, bool enable); |
85 | extern void cik_sdma_fini(struct radeon_device *rdev); | 86 | extern void cik_sdma_fini(struct radeon_device *rdev); |
@@ -3257,7 +3258,7 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
3257 | u32 mc_shared_chmap, mc_arb_ramcfg; | 3258 | u32 mc_shared_chmap, mc_arb_ramcfg; |
3258 | u32 hdp_host_path_cntl; | 3259 | u32 hdp_host_path_cntl; |
3259 | u32 tmp; | 3260 | u32 tmp; |
3260 | int i, j; | 3261 | int i, j, k; |
3261 | 3262 | ||
3262 | switch (rdev->family) { | 3263 | switch (rdev->family) { |
3263 | case CHIP_BONAIRE: | 3264 | case CHIP_BONAIRE: |
@@ -3446,6 +3447,15 @@ static void cik_gpu_init(struct radeon_device *rdev) | |||
3446 | rdev->config.cik.max_sh_per_se, | 3447 | rdev->config.cik.max_sh_per_se, |
3447 | rdev->config.cik.max_backends_per_se); | 3448 | rdev->config.cik.max_backends_per_se); |
3448 | 3449 | ||
3450 | for (i = 0; i < rdev->config.cik.max_shader_engines; i++) { | ||
3451 | for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { | ||
3452 | for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) { | ||
3453 | rdev->config.cik.active_cus += | ||
3454 | hweight32(cik_get_cu_active_bitmap(rdev, i, j)); | ||
3455 | } | ||
3456 | } | ||
3457 | } | ||
3458 | |||
3449 | /* set HW defaults for 3D engine */ | 3459 | /* set HW defaults for 3D engine */ |
3450 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); | 3460 | WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60)); |
3451 | 3461 | ||