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authorAlex Deucher <alexander.deucher@amd.com>2011-10-28 18:34:20 -0400
committerDave Airlie <airlied@redhat.com>2011-11-01 12:05:17 -0400
commit58cdcb8bbe867aa86bbd5f097086d82330a7182f (patch)
tree25eb085cb66d1fef5d79361f7a8cebe1cadd71d0 /drivers/gpu/drm/radeon/atombios_encoders.c
parent24153dd35edda344936ebf0f00ce477f7ed7df3b (diff)
drm/radeon/kms: make atombios_dig_encoder_setup() version based
set up the params based on the table version number. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_encoders.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c211
1 files changed, 127 insertions, 84 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 7d91d3ca9c69..e0285c419875 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -585,97 +585,140 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev)) 585 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
586 return; 586 return;
587 587
588 args.v1.ucAction = action; 588 switch (frev) {
589 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); 589 case 1:
590 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE) 590 switch (crev) {
591 args.v3.ucPanelMode = panel_mode; 591 case 1:
592 else 592 args.v1.ucAction = action;
593 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder); 593 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
594 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
595 args.v3.ucPanelMode = panel_mode;
596 else
597 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
594 598
595 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) 599 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
596 args.v1.ucLaneNum = dp_lane_count; 600 args.v1.ucLaneNum = dp_lane_count;
597 else if (radeon_encoder->pixel_clock > 165000) 601 else if (radeon_encoder->pixel_clock > 165000)
598 args.v1.ucLaneNum = 8; 602 args.v1.ucLaneNum = 8;
599 else 603 else
600 args.v1.ucLaneNum = 4; 604 args.v1.ucLaneNum = 4;
601 605
602 if (ASIC_IS_DCE5(rdev)) { 606 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
603 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) { 607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
604 if (dp_clock == 270000) 608 switch (radeon_encoder->encoder_id) {
605 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ; 609 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
606 else if (dp_clock == 540000) 610 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
607 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ; 611 break;
608 } 612 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
609 args.v4.acConfig.ucDigSel = dig->dig_encoder; 613 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
610 switch (bpc) { 614 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
611 case 0: 615 break;
612 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE; 616 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
613 break; 617 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
614 case 6: 618 break;
615 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR; 619 }
616 break; 620 if (dig->linkb)
617 case 8: 621 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
618 default: 622 else
619 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR; 623 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
620 break;
621 case 10:
622 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
623 break;
624 case 12:
625 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
626 break;
627 case 16:
628 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
629 break; 624 break;
630 } 625 case 2:
631 if (hpd_id == RADEON_HPD_NONE) 626 case 3:
632 args.v4.ucHPD_ID = 0; 627 args.v3.ucAction = action;
633 else 628 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
634 args.v4.ucHPD_ID = hpd_id + 1; 629 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
635 } else if (ASIC_IS_DCE4(rdev)) { 630 args.v3.ucPanelMode = panel_mode;
636 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000)) 631 else
637 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ; 632 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
638 args.v3.acConfig.ucDigSel = dig->dig_encoder; 633
639 switch (bpc) { 634 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
640 case 0: 635 args.v3.ucLaneNum = dp_lane_count;
641 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE; 636 else if (radeon_encoder->pixel_clock > 165000)
637 args.v3.ucLaneNum = 8;
638 else
639 args.v3.ucLaneNum = 4;
640
641 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
642 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
643 args.v3.acConfig.ucDigSel = dig->dig_encoder;
644 switch (bpc) {
645 case 0:
646 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
647 break;
648 case 6:
649 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
650 break;
651 case 8:
652 default:
653 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
654 break;
655 case 10:
656 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
657 break;
658 case 12:
659 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
660 break;
661 case 16:
662 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
663 break;
664 }
642 break; 665 break;
643 case 6: 666 case 4:
644 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR; 667 args.v4.ucAction = action;
668 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
669 if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
670 args.v4.ucPanelMode = panel_mode;
671 else
672 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
673
674 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
675 args.v4.ucLaneNum = dp_lane_count;
676 else if (radeon_encoder->pixel_clock > 165000)
677 args.v4.ucLaneNum = 8;
678 else
679 args.v4.ucLaneNum = 4;
680
681 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
682 if (dp_clock == 270000)
683 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
684 else if (dp_clock == 540000)
685 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
686 }
687 args.v4.acConfig.ucDigSel = dig->dig_encoder;
688 switch (bpc) {
689 case 0:
690 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
691 break;
692 case 6:
693 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
694 break;
695 case 8:
696 default:
697 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
698 break;
699 case 10:
700 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
701 break;
702 case 12:
703 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
704 break;
705 case 16:
706 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
707 break;
708 }
709 if (hpd_id == RADEON_HPD_NONE)
710 args.v4.ucHPD_ID = 0;
711 else
712 args.v4.ucHPD_ID = hpd_id + 1;
645 break; 713 break;
646 case 8:
647 default: 714 default:
648 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR; 715 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
649 break;
650 case 10:
651 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
652 break;
653 case 12:
654 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
655 break;
656 case 16:
657 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
658 break;
659 }
660 } else {
661 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
662 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
663 switch (radeon_encoder->encoder_id) {
664 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
665 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
666 break;
667 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
669 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
670 break;
671 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
672 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
673 break; 716 break;
674 } 717 }
675 if (dig->linkb) 718 break;
676 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB; 719 default:
677 else 720 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
678 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA; 721 break;
679 } 722 }
680 723
681 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 724 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 04:52:46 -0500