drm/radeon: Add support for programming the FMT blocks

The FMT blocks control how data is sent from the backend
of the display pipe to to monitor.  Proper set up of the
FMT blocks are required for 30bpp formats.  Additionally,
dithering can be enabled on for better display with 18 and
24bpp displays.  The exception is LVDS/eDP which atom
takes care of in the SelectCRTC_Source table.  For now
just enable truncation until we test dithering more.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 28e2dc48e015..ffd99737014b 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2392,6 +2392,15 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 
         /* this is needed for the pll/ss setup to work correctly in some cases */
         atombios_set_encoder_crtc_source(encoder);
+        /* set up the FMT blocks */
+        if (ASIC_IS_DCE8(rdev))
+                dce8_program_fmt(encoder);
+        else if (ASIC_IS_DCE4(rdev))
+                dce4_program_fmt(encoder);
+        else if (ASIC_IS_DCE3(rdev))
+                dce3_program_fmt(encoder);
+        else if (ASIC_IS_AVIVO(rdev))
+                avivo_program_fmt(encoder);
 }
 
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)