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authorAlex Deucher <alexdeucher@gmail.com>2009-11-24 13:32:59 -0500
committerDave Airlie <airlied@redhat.com>2009-12-07 19:22:44 -0500
commit5801ead6bd6bddf5505d6eab55f84d8ee8106cd8 (patch)
tree60cc75789c50aab78299499e05411c9140616bc2 /drivers/gpu/drm/radeon/atombios_dp.c
parentf92a8b6758bdc0f277c4f42aa7d736a205ac9ded (diff)
drm/radeon/kms: add support for DP modesetting
Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_dp.c')
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c541
1 files changed, 488 insertions, 53 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 76eb5c8a7016..ebaf3f8cd602 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -31,9 +31,20 @@
31#include "atom-bits.h" 31#include "atom-bits.h"
32#include "drm_dp_helper.h" 32#include "drm_dp_helper.h"
33 33
34#define DP_LINK_STATUS_SIZE 6
35
36/* move these to drm_dp_helper.c/h */ 34/* move these to drm_dp_helper.c/h */
35#define DP_LINK_CONFIGURATION_SIZE 9
36#define DP_LINK_STATUS_SIZE 6
37#define DP_DPCD_SIZE 8
38
39static char *voltage_names[] = {
40 "0.4V", "0.6V", "0.8V", "1.2V"
41};
42static char *pre_emph_names[] = {
43 "0dB", "3.5dB", "6dB", "9.5dB"
44};
45static char *link_train_names[] = {
46 "pattern 1", "pattern 2", "idle", "off"
47};
37 48
38static const int dp_clocks[] = { 49static const int dp_clocks[] = {
39 54000, // 1 lane, 1.62 Ghz 50 54000, // 1 lane, 1.62 Ghz
@@ -46,9 +57,18 @@ static const int dp_clocks[] = {
46 57
47static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int); 58static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
48 59
49int dp_lanes_for_mode_clock(int max_link_bw, int mode_clock) 60/* common helper functions */
61static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
50{ 62{
51 int i; 63 int i;
64 u8 max_link_bw;
65 u8 max_lane_count;
66
67 if (!dpcd)
68 return 0;
69
70 max_link_bw = dpcd[DP_MAX_LINK_RATE];
71 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
52 72
53 switch (max_link_bw) { 73 switch (max_link_bw) {
54 case DP_LINK_BW_1_62: 74 case DP_LINK_BW_1_62:
@@ -56,6 +76,19 @@ int dp_lanes_for_mode_clock(int max_link_bw, int mode_clock)
56 for (i = 0; i < num_dp_clocks; i++) { 76 for (i = 0; i < num_dp_clocks; i++) {
57 if (i % 2) 77 if (i % 2)
58 continue; 78 continue;
79 switch (max_lane_count) {
80 case 1:
81 if (i > 1)
82 return 0;
83 break;
84 case 2:
85 if (i > 3)
86 return 0;
87 break;
88 case 4:
89 default:
90 break;
91 }
59 if (dp_clocks[i] > mode_clock) { 92 if (dp_clocks[i] > mode_clock) {
60 if (i < 2) 93 if (i < 2)
61 return 1; 94 return 1;
@@ -68,6 +101,19 @@ int dp_lanes_for_mode_clock(int max_link_bw, int mode_clock)
68 break; 101 break;
69 case DP_LINK_BW_2_7: 102 case DP_LINK_BW_2_7:
70 for (i = 0; i < num_dp_clocks; i++) { 103 for (i = 0; i < num_dp_clocks; i++) {
104 switch (max_lane_count) {
105 case 1:
106 if (i > 1)
107 return 0;
108 break;
109 case 2:
110 if (i > 3)
111 return 0;
112 break;
113 case 4:
114 default:
115 break;
116 }
71 if (dp_clocks[i] > mode_clock) { 117 if (dp_clocks[i] > mode_clock) {
72 if (i < 2) 118 if (i < 2)
73 return 1; 119 return 1;
@@ -83,17 +129,56 @@ int dp_lanes_for_mode_clock(int max_link_bw, int mode_clock)
83 return 0; 129 return 0;
84} 130}
85 131
86int dp_link_clock_for_mode_clock(int max_link_bw, int mode_clock) 132static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
87{ 133{
88 int i; 134 int i;
135 u8 max_link_bw;
136 u8 max_lane_count;
137
138 if (!dpcd)
139 return 0;
140
141 max_link_bw = dpcd[DP_MAX_LINK_RATE];
142 max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
89 143
90 switch (max_link_bw) { 144 switch (max_link_bw) {
91 case DP_LINK_BW_1_62: 145 case DP_LINK_BW_1_62:
92 default: 146 default:
93 return 162000; 147 for (i = 0; i < num_dp_clocks; i++) {
148 if (i % 2)
149 continue;
150 switch (max_lane_count) {
151 case 1:
152 if (i > 1)
153 return 0;
154 break;
155 case 2:
156 if (i > 3)
157 return 0;
158 break;
159 case 4:
160 default:
161 break;
162 }
163 if (dp_clocks[i] > mode_clock)
164 return 162000;
165 }
94 break; 166 break;
95 case DP_LINK_BW_2_7: 167 case DP_LINK_BW_2_7:
96 for (i = 0; i < num_dp_clocks; i++) { 168 for (i = 0; i < num_dp_clocks; i++) {
169 switch (max_lane_count) {
170 case 1:
171 if (i > 1)
172 return 0;
173 break;
174 case 2:
175 if (i > 3)
176 return 0;
177 break;
178 case 4:
179 default:
180 break;
181 }
97 if (dp_clocks[i] > mode_clock) 182 if (dp_clocks[i] > mode_clock)
98 return (i % 2) ? 270000 : 162000; 183 return (i % 2) ? 270000 : 162000;
99 } 184 }
@@ -102,6 +187,145 @@ int dp_link_clock_for_mode_clock(int max_link_bw, int mode_clock)
102 return 0; 187 return 0;
103} 188}
104 189
190int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
191{
192 int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
193 int bw = dp_lanes_for_mode_clock(dpcd, mode_clock);
194
195 if ((lanes == 0) || (bw == 0))
196 return MODE_CLOCK_HIGH;
197
198 return MODE_OK;
199}
200
201static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
202{
203 return link_status[r - DP_LANE0_1_STATUS];
204}
205
206static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
207 int lane)
208{
209 int i = DP_LANE0_1_STATUS + (lane >> 1);
210 int s = (lane & 1) * 4;
211 u8 l = dp_link_status(link_status, i);
212 return (l >> s) & 0xf;
213}
214
215static bool dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
216 int lane_count)
217{
218 int lane;
219 u8 lane_status;
220
221 for (lane = 0; lane < lane_count; lane++) {
222 lane_status = dp_get_lane_status(link_status, lane);
223 if ((lane_status & DP_LANE_CR_DONE) == 0)
224 return false;
225 }
226 return true;
227}
228
229static bool dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
230 int lane_count)
231{
232 u8 lane_align;
233 u8 lane_status;
234 int lane;
235
236 lane_align = dp_link_status(link_status,
237 DP_LANE_ALIGN_STATUS_UPDATED);
238 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
239 return false;
240 for (lane = 0; lane < lane_count; lane++) {
241 lane_status = dp_get_lane_status(link_status, lane);
242 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
243 return false;
244 }
245 return true;
246}
247
248static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
249 int lane)
250
251{
252 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
253 int s = ((lane & 1) ?
254 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
255 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
256 u8 l = dp_link_status(link_status, i);
257
258 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
259}
260
261static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
262 int lane)
263{
264 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
265 int s = ((lane & 1) ?
266 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
267 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
268 u8 l = dp_link_status(link_status, i);
269
270 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
271}
272
273/* XXX fix me -- chip specific */
274#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
275static u8 dp_pre_emphasis_max(u8 voltage_swing)
276{
277 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
278 case DP_TRAIN_VOLTAGE_SWING_400:
279 return DP_TRAIN_PRE_EMPHASIS_6;
280 case DP_TRAIN_VOLTAGE_SWING_600:
281 return DP_TRAIN_PRE_EMPHASIS_6;
282 case DP_TRAIN_VOLTAGE_SWING_800:
283 return DP_TRAIN_PRE_EMPHASIS_3_5;
284 case DP_TRAIN_VOLTAGE_SWING_1200:
285 default:
286 return DP_TRAIN_PRE_EMPHASIS_0;
287 }
288}
289
290static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
291 int lane_count,
292 u8 train_set[4])
293{
294 u8 v = 0;
295 u8 p = 0;
296 int lane;
297
298 for (lane = 0; lane < lane_count; lane++) {
299 u8 this_v = dp_get_adjust_request_voltage(link_status, lane);
300 u8 this_p = dp_get_adjust_request_pre_emphasis(link_status, lane);
301
302 DRM_INFO("requested signal parameters: lane %d voltage %s pre_emph %s\n",
303 lane,
304 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
305 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
306
307 if (this_v > v)
308 v = this_v;
309 if (this_p > p)
310 p = this_p;
311 }
312
313 if (v >= DP_VOLTAGE_MAX)
314 v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
315
316 if (p >= dp_pre_emphasis_max(v))
317 p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
318
319 DRM_INFO("using signal parameters: voltage %s pre_emph %s\n",
320 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
321 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
322
323 for (lane = 0; lane < 4; lane++)
324 train_set[lane] = v | p;
325}
326
327
328/* radeon aux chan functions */
105bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes, 329bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
106 int num_bytes, u8 *read_byte, 330 int num_bytes, u8 *read_byte,
107 u8 read_buf_len, u8 delay) 331 u8 read_buf_len, u8 delay)
@@ -147,44 +371,10 @@ bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
147 return true; 371 return true;
148} 372}
149 373
150static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
151 uint8_t ucconfig, uint8_t lane_num)
152{
153 DP_ENCODER_SERVICE_PARAMETERS args;
154 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
155
156 memset(&args, 0, sizeof(args));
157 args.ucLinkClock = dp_clock / 10;
158 args.ucConfig = ucconfig;
159 args.ucAction = action;
160 args.ucLaneNum = lane_num;
161 args.ucStatus = 0;
162
163 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
164 return args.ucStatus;
165}
166
167u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
168{
169 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
170 struct drm_device *dev = radeon_connector->base.dev;
171 struct radeon_device *rdev = dev->dev_private;
172
173 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
174 radeon_dig_connector->dp_i2c_bus->rec.i2c_id, 0);
175}
176
177union dig_transmitter_control {
178 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
179 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
180};
181
182bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address, 374bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
183 uint8_t send_bytes, uint8_t *send) 375 uint8_t send_bytes, uint8_t *send)
184{ 376{
185 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 377 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
186 struct drm_device *dev = radeon_connector->base.dev;
187 struct radeon_device *rdev = dev->dev_private;
188 u8 msg[20]; 378 u8 msg[20];
189 u8 msg_len, dp_msg_len; 379 u8 msg_len, dp_msg_len;
190 bool ret; 380 bool ret;
@@ -201,7 +391,7 @@ bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint1
201 391
202 memcpy(&msg[4], send, send_bytes); 392 memcpy(&msg[4], send, send_bytes);
203 msg_len = 4 + send_bytes; 393 msg_len = 4 + send_bytes;
204 ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0); 394 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
205 return ret; 395 return ret;
206} 396}
207 397
@@ -209,9 +399,7 @@ bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16
209 uint8_t delay, uint8_t expected_bytes, 399 uint8_t delay, uint8_t expected_bytes,
210 uint8_t *read_p) 400 uint8_t *read_p)
211{ 401{
212 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 402 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
213 struct drm_device *dev = radeon_connector->base.dev;
214 struct radeon_device *rdev = dev->dev_private;
215 u8 msg[20]; 403 u8 msg[20];
216 u8 msg_len, dp_msg_len; 404 u8 msg_len, dp_msg_len;
217 bool ret = false; 405 bool ret = false;
@@ -223,19 +411,47 @@ bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16
223 msg[3] = (dp_msg_len) << 4; 411 msg[3] = (dp_msg_len) << 4;
224 msg[3] |= expected_bytes - 1; 412 msg[3] |= expected_bytes - 1;
225 413
226 ret = radeon_process_aux_ch(radeon_dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay); 414 ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
227 return ret; 415 return ret;
228} 416}
229 417
418/* radeon dp functions */
419static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
420 uint8_t ucconfig, uint8_t lane_num)
421{
422 DP_ENCODER_SERVICE_PARAMETERS args;
423 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
424
425 memset(&args, 0, sizeof(args));
426 args.ucLinkClock = dp_clock / 10;
427 args.ucConfig = ucconfig;
428 args.ucAction = action;
429 args.ucLaneNum = lane_num;
430 args.ucStatus = 0;
431
432 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
433 return args.ucStatus;
434}
435
436u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector)
437{
438 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
439 struct drm_device *dev = radeon_connector->base.dev;
440 struct radeon_device *rdev = dev->dev_private;
441
442 return radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
443 dig_connector->dp_i2c_bus->rec.i2c_id, 0);
444}
445
230void radeon_dp_getdpcd(struct radeon_connector *radeon_connector) 446void radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
231{ 447{
232 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 448 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
233 u8 msg[25]; 449 u8 msg[25];
234 int ret; 450 int ret;
235 451
236 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg); 452 ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
237 if (ret) { 453 if (ret) {
238 memcpy(radeon_dig_connector->dpcd, msg, 8); 454 memcpy(dig_connector->dpcd, msg, 8);
239 { 455 {
240 int i; 456 int i;
241 printk("DPCD: "); 457 printk("DPCD: ");
@@ -244,10 +460,38 @@ void radeon_dp_getdpcd(struct radeon_connector *radeon_connector)
244 printk("\n"); 460 printk("\n");
245 } 461 }
246 } 462 }
247 radeon_dig_connector->dpcd[0] = 0; 463 dig_connector->dpcd[0] = 0;
248 return; 464 return;
249} 465}
250 466
467void radeon_dp_set_link_config(struct drm_connector *connector,
468 struct drm_display_mode *mode)
469{
470 struct radeon_connector *radeon_connector;
471 struct radeon_connector_atom_dig *dig_connector;
472
473 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
474 return;
475
476 radeon_connector = to_radeon_connector(connector);
477 if (!radeon_connector->con_priv)
478 return;
479 dig_connector = radeon_connector->con_priv;
480
481 dig_connector->dp_clock =
482 dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
483 dig_connector->dp_lane_count =
484 dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
485}
486
487int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
488 struct drm_display_mode *mode)
489{
490 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
491
492 return dp_mode_valid(dig_connector->dpcd, mode->clock);
493}
494
251static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector, 495static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
252 u8 link_status[DP_LINK_STATUS_SIZE]) 496 u8 link_status[DP_LINK_STATUS_SIZE])
253{ 497{
@@ -267,21 +511,41 @@ static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
267 511
268static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state) 512static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
269{ 513{
270 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 514 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
271 if (radeon_dig_connector->dpcd[0] >= 0x11) { 515
516 if (dig_connector->dpcd[0] >= 0x11) {
272 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1, 517 radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
273 &power_state); 518 &power_state);
274 } 519 }
275} 520}
276 521
522static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
523{
524 radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
525 &downspread);
526}
527
528static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
529 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
530{
531 radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
532 link_configuration);
533}
534
277static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector, 535static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
536 struct drm_encoder *encoder,
278 u8 train_set[4]) 537 u8 train_set[4])
279{ 538{
280 struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; 539 struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
540 int i;
541
542 for (i = 0; i < dig_connector->dp_lane_count; i++)
543 atombios_dig_transmitter_setup(encoder,
544 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
545 i, train_set[i]);
281 546
282// radeon_dp_digtransmitter_setup_vsemph();
283 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET, 547 radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
284 0/* lc */, train_set); 548 dig_connector->dp_lane_count, train_set);
285} 549}
286 550
287static void dp_set_training(struct radeon_connector *radeon_connector, 551static void dp_set_training(struct radeon_connector *radeon_connector,
@@ -291,6 +555,176 @@ static void dp_set_training(struct radeon_connector *radeon_connector,
291 1, &training); 555 1, &training);
292} 556}
293 557
558void dp_link_train(struct drm_encoder *encoder,
559 struct drm_connector *connector)
560{
561 struct drm_device *dev = encoder->dev;
562 struct radeon_device *rdev = dev->dev_private;
563 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
564 struct radeon_encoder_atom_dig *dig;
565 struct radeon_connector *radeon_connector;
566 struct radeon_connector_atom_dig *dig_connector;
567 int enc_id = 0;
568 bool clock_recovery, channel_eq;
569 u8 link_status[DP_LINK_STATUS_SIZE];
570 u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
571 u8 tries, voltage;
572 u8 train_set[4];
573 int i;
574
575 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
576 return;
577
578 if (!radeon_encoder->enc_priv)
579 return;
580 dig = radeon_encoder->enc_priv;
581
582 radeon_connector = to_radeon_connector(connector);
583 if (!radeon_connector->con_priv)
584 return;
585 dig_connector = radeon_connector->con_priv;
586
587 if (ASIC_IS_DCE32(rdev)) {
588 if (dig->dig_block)
589 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
590 else
591 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
592 if (dig_connector->linkb)
593 enc_id |= ATOM_DP_CONFIG_LINK_B;
594 else
595 enc_id |= ATOM_DP_CONFIG_LINK_A;
596 } else {
597 if (dig_connector->linkb)
598 enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER | ATOM_DP_CONFIG_LINK_B;
599 else
600 enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER | ATOM_DP_CONFIG_LINK_A;
601 }
602
603 memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
604 if (dig_connector->dp_clock == 270000)
605 link_configuration[0] = DP_LINK_BW_2_7;
606 else
607 link_configuration[0] = DP_LINK_BW_1_62;
608 link_configuration[1] = dig_connector->dp_lane_count;
609 if (dig_connector->dpcd[0] >= 0x11)
610 link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
611
612 /* power up the sink */
613 dp_set_power(radeon_connector, DP_SET_POWER_D0);
614 /* disable the training pattern on the sink */
615 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
616 /* set link bw and lanes on the sink */
617 dp_set_link_bw_lanes(radeon_connector, link_configuration);
618 /* disable downspread on the sink */
619 dp_set_downspread(radeon_connector, 0);
620 /* start training on the source */
621 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
622 dig_connector->dp_clock, enc_id, 0);
623 /* set training pattern 1 on the source */
624 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
625 dig_connector->dp_clock, enc_id, 0);
626
627 /* set initial vs/emph */
628 memset(train_set, 0, 4);
629 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
630 udelay(400);
631 /* set training pattern 1 on the sink */
632 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
633
634 /* clock recovery loop */
635 clock_recovery = false;
636 tries = 0;
637 voltage = 0xff;
638 for (;;) {
639 udelay(100);
640 if (!atom_dp_get_link_status(radeon_connector, link_status))
641 break;
642
643 if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
644 clock_recovery = true;
645 break;
646 }
647
648 for (i = 0; i < dig_connector->dp_lane_count; i++) {
649 if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
650 break;
651 }
652 if (i == dig_connector->dp_lane_count) {
653 DRM_ERROR("clock recovery reached max voltage\n");
654 break;
655 }
656
657 if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
658 ++tries;
659 if (tries == 5) {
660 DRM_ERROR("clock recovery tried 5 times\n");
661 break;
662 }
663 } else
664 tries = 0;
665
666 voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
667
668 /* Compute new train_set as requested by sink */
669 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
670 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
671 }
672 if (!clock_recovery)
673 DRM_ERROR("clock recovery failed\n");
674 else
675 DRM_INFO("clock recovery at voltage %d pre-emphasis %d\n",
676 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
677 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
678 DP_TRAIN_PRE_EMPHASIS_SHIFT);
679
680
681 /* set training pattern 2 on the sink */
682 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
683 /* set training pattern 2 on the source */
684 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
685 dig_connector->dp_clock, enc_id, 1);
686
687 /* channel equalization loop */
688 tries = 0;
689 channel_eq = false;
690 for (;;) {
691 udelay(400);
692 if (!atom_dp_get_link_status(radeon_connector, link_status))
693 break;
694
695 if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
696 channel_eq = true;
697 break;
698 }
699
700 /* Try 5 times */
701 if (tries > 5) {
702 DRM_ERROR("channel eq failed: 5 tries\n");
703 break;
704 }
705
706 /* Compute new train_set as requested by sink */
707 dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
708 dp_update_dpvs_emph(radeon_connector, encoder, train_set);
709
710 tries++;
711 }
712
713 if (!channel_eq)
714 DRM_ERROR("channel eq failed\n");
715 else
716 DRM_INFO("channel eq at voltage %d pre-emphasis %d\n",
717 train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
718 (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
719 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
720
721 /* disable the training pattern on the sink */
722 dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
723
724 radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
725 dig_connector->dp_clock, enc_id, 0);
726}
727
294int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, 728int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
295 uint8_t write_byte, uint8_t *read_byte) 729 uint8_t write_byte, uint8_t *read_byte)
296{ 730{
@@ -342,3 +776,4 @@ int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
342 } 776 }
343 return -EREMOTEIO; 777 return -EREMOTEIO;
344} 778}
779