drm/radeon/kms: add initial colortiling support.

This adds new set/get tiling interfaces where the pitch
and macro/micro tiling enables can be set. Along with
a flag to decide if this object should have a surface when mapped.

The only thing we need to allocate with a mapped surface should be
the frontbuffer. Note rotate scanout shouldn't require one, and
back/depth shouldn't either, though mesa needs some fixes.

It fixes the TTM interfaces along Thomas's suggestions, and I've tested
the surface stealing code with two X servers and not seen any lockdep issues.

I've stopped tiling the fbcon frontbuffer, as I don't see there being
any advantage other than testing, I've left the testing commands in there,
just flip the fb_tiled to true in radeon_fb.c

Open: Can we integrate endian swapping in with this?

Future features:
texture tiling - need to relocate texture registers TXOFFSET* with tiling info.

This also merges Michel's cleanup surfaces regs at init time patch
even though it makes sense on its own, this patch really relies on it.

Some PowerMac firmwares set up a tiling surface at the beginning of VRAM
which messes us up otherwise.
that patch is:
Signed-off-by: Michel Dänzer <daenzer@vmware.com>

Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index e64a199b5ee1..eac26cdb5dae 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -327,7 +327,7 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
         struct drm_gem_object *obj;
         struct drm_radeon_gem_object *obj_priv;
         uint64_t fb_location;
-        uint32_t fb_format, fb_pitch_pixels;
+        uint32_t fb_format, fb_pitch_pixels, tiling_flags;
 
         if (!crtc->fb)
                 return -EINVAL;
@@ -364,7 +364,14 @@ int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
                 return -EINVAL;
         }
 
-        /* TODO tiling */
+        radeon_object_get_tiling_flags(obj->driver_private,
+                                       &tiling_flags, NULL);
+        if (tiling_flags & RADEON_TILING_MACRO)
+                fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
+
+        if (tiling_flags & RADEON_TILING_MICRO)
+                fb_format |= AVIVO_D1GRPH_TILED;
+
         if (radeon_crtc->crtc_id == 0)
                 WREG32(AVIVO_D1VGA_CONTROL, 0);
         else