drm/radeon: SI tiling fixes for display

- Use the correct union for getting the tiling info
- Properly init the PIPE_CONFIG field for SI

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

1 files changed, 9 insertions, 1 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 01d77d1554f4..3904d7964a4b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1149,7 +1149,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         }
 
         if (tiling_flags & RADEON_TILING_MACRO) {
-                if (rdev->family >= CHIP_CAYMAN)
+                if (rdev->family >= CHIP_TAHITI)
+                        tmp = rdev->config.si.tile_config;
+                else if (rdev->family >= CHIP_CAYMAN)
                         tmp = rdev->config.cayman.tile_config;
                 else
                         tmp = rdev->config.evergreen.tile_config;
@@ -1177,6 +1179,12 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
         } else if (tiling_flags & RADEON_TILING_MICRO)
                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
 
+        if ((rdev->family == CHIP_TAHITI) ||
+            (rdev->family == CHIP_PITCAIRN))
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
+        else if (rdev->family == CHIP_VERDE)
+                fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
+
         switch (radeon_crtc->crtc_id) {
         case 0:
                 WREG32(AVIVO_D1VGA_CONTROL, 0);