diff options
author | Alex Deucher <alexdeucher@gmail.com> | 2010-11-22 17:56:20 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2010-11-22 18:23:16 -0500 |
commit | 1422ef52efa2b9abcf8e9d4d641f3a12579f1027 (patch) | |
tree | f1c5043c57f3f0374d3698d559010ca79f7a5cc8 /drivers/gpu/drm/radeon/atombios.h | |
parent | 5d68e501bf000b8b1696875455c7a556ce2e9c43 (diff) |
drm/radeon/kms: upstream atombios.h updates
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios.h')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios.h | 853 |
1 files changed, 792 insertions, 61 deletions
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h index fe359a239df3..6a9baa2443f8 100644 --- a/drivers/gpu/drm/radeon/atombios.h +++ b/drivers/gpu/drm/radeon/atombios.h | |||
@@ -73,8 +73,18 @@ | |||
73 | #define ATOM_PPLL1 0 | 73 | #define ATOM_PPLL1 0 |
74 | #define ATOM_PPLL2 1 | 74 | #define ATOM_PPLL2 1 |
75 | #define ATOM_DCPLL 2 | 75 | #define ATOM_DCPLL 2 |
76 | #define ATOM_PPLL0 2 | ||
77 | #define ATOM_EXT_PLL1 8 | ||
78 | #define ATOM_EXT_PLL2 9 | ||
79 | #define ATOM_EXT_CLOCK 10 | ||
76 | #define ATOM_PPLL_INVALID 0xFF | 80 | #define ATOM_PPLL_INVALID 0xFF |
77 | 81 | ||
82 | #define ENCODER_REFCLK_SRC_P1PLL 0 | ||
83 | #define ENCODER_REFCLK_SRC_P2PLL 1 | ||
84 | #define ENCODER_REFCLK_SRC_DCPLL 2 | ||
85 | #define ENCODER_REFCLK_SRC_EXTCLK 3 | ||
86 | #define ENCODER_REFCLK_SRC_INVALID 0xFF | ||
87 | |||
78 | #define ATOM_SCALER1 0 | 88 | #define ATOM_SCALER1 0 |
79 | #define ATOM_SCALER2 1 | 89 | #define ATOM_SCALER2 1 |
80 | 90 | ||
@@ -192,6 +202,9 @@ typedef struct _ATOM_COMMON_TABLE_HEADER | |||
192 | /*Image can't be updated, while Driver needs to carry the new table! */ | 202 | /*Image can't be updated, while Driver needs to carry the new table! */ |
193 | }ATOM_COMMON_TABLE_HEADER; | 203 | }ATOM_COMMON_TABLE_HEADER; |
194 | 204 | ||
205 | /****************************************************************************/ | ||
206 | // Structure stores the ROM header. | ||
207 | /****************************************************************************/ | ||
195 | typedef struct _ATOM_ROM_HEADER | 208 | typedef struct _ATOM_ROM_HEADER |
196 | { | 209 | { |
197 | ATOM_COMMON_TABLE_HEADER sHeader; | 210 | ATOM_COMMON_TABLE_HEADER sHeader; |
@@ -221,6 +234,9 @@ typedef struct _ATOM_ROM_HEADER | |||
221 | #define USHORT void* | 234 | #define USHORT void* |
222 | #endif | 235 | #endif |
223 | 236 | ||
237 | /****************************************************************************/ | ||
238 | // Structures used in Command.mtb | ||
239 | /****************************************************************************/ | ||
224 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ | 240 | typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ |
225 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 | 241 | USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 |
226 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON | 242 | USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON |
@@ -312,6 +328,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ | |||
312 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange | 328 | #define SetUniphyInstance ASIC_StaticPwrMgtStatusChange |
313 | #define HPDInterruptService ReadHWAssistedI2CStatus | 329 | #define HPDInterruptService ReadHWAssistedI2CStatus |
314 | #define EnableVGA_Access GetSCLKOverMCLKRatio | 330 | #define EnableVGA_Access GetSCLKOverMCLKRatio |
331 | #define GetDispObjectInfo EnableYUV | ||
315 | 332 | ||
316 | typedef struct _ATOM_MASTER_COMMAND_TABLE | 333 | typedef struct _ATOM_MASTER_COMMAND_TABLE |
317 | { | 334 | { |
@@ -357,6 +374,24 @@ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER | |||
357 | /****************************************************************************/ | 374 | /****************************************************************************/ |
358 | #define COMPUTE_MEMORY_PLL_PARAM 1 | 375 | #define COMPUTE_MEMORY_PLL_PARAM 1 |
359 | #define COMPUTE_ENGINE_PLL_PARAM 2 | 376 | #define COMPUTE_ENGINE_PLL_PARAM 2 |
377 | #define ADJUST_MC_SETTING_PARAM 3 | ||
378 | |||
379 | /****************************************************************************/ | ||
380 | // Structures used by AdjustMemoryControllerTable | ||
381 | /****************************************************************************/ | ||
382 | typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ | ||
383 | { | ||
384 | #if ATOM_BIG_ENDIAN | ||
385 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block | ||
386 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] | ||
387 | ULONG ulClockFreq:24; | ||
388 | #else | ||
389 | ULONG ulClockFreq:24; | ||
390 | ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] | ||
391 | ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block | ||
392 | #endif | ||
393 | }ATOM_ADJUST_MEMORY_CLOCK_FREQ; | ||
394 | #define POINTER_RETURN_FLAG 0x80 | ||
360 | 395 | ||
361 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS | 396 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS |
362 | { | 397 | { |
@@ -440,6 +475,26 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 | |||
440 | #endif | 475 | #endif |
441 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; | 476 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; |
442 | 477 | ||
478 | typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 | ||
479 | { | ||
480 | union | ||
481 | { | ||
482 | ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter | ||
483 | ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter | ||
484 | }; | ||
485 | UCHAR ucRefDiv; //Output Parameter | ||
486 | UCHAR ucPostDiv; //Output Parameter | ||
487 | union | ||
488 | { | ||
489 | UCHAR ucCntlFlag; //Output Flags | ||
490 | UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode | ||
491 | }; | ||
492 | UCHAR ucReserved; | ||
493 | }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; | ||
494 | |||
495 | // ucInputFlag | ||
496 | #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode | ||
497 | |||
443 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER | 498 | typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER |
444 | { | 499 | { |
445 | ATOM_COMPUTE_CLOCK_FREQ ulClock; | 500 | ATOM_COMPUTE_CLOCK_FREQ ulClock; |
@@ -583,6 +638,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS | |||
583 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 | 638 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 |
584 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 | 639 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 |
585 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 | 640 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 |
641 | #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 | ||
586 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 | 642 | #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 |
587 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 | 643 | #define ATOM_ENCODER_CONFIG_LINKA 0x00 |
588 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 | 644 | #define ATOM_ENCODER_CONFIG_LINKB 0x04 |
@@ -608,6 +664,9 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS | |||
608 | #define ATOM_ENCODER_MODE_TV 13 | 664 | #define ATOM_ENCODER_MODE_TV 13 |
609 | #define ATOM_ENCODER_MODE_CV 14 | 665 | #define ATOM_ENCODER_MODE_CV 14 |
610 | #define ATOM_ENCODER_MODE_CRT 15 | 666 | #define ATOM_ENCODER_MODE_CRT 15 |
667 | #define ATOM_ENCODER_MODE_DVO 16 | ||
668 | #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 | ||
669 | #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 | ||
611 | 670 | ||
612 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 | 671 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 |
613 | { | 672 | { |
@@ -661,6 +720,7 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 | |||
661 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 | 720 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 |
662 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 | 721 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 |
663 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a | 722 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a |
723 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 | ||
664 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b | 724 | #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b |
665 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c | 725 | #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c |
666 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d | 726 | #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d |
@@ -671,24 +731,34 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 | |||
671 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 | 731 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 |
672 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 | 732 | #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 |
673 | 733 | ||
734 | //ucTableFormatRevision=1 | ||
735 | //ucTableContentRevision=3 | ||
674 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver | 736 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver |
675 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 | 737 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 |
676 | { | 738 | { |
677 | #if ATOM_BIG_ENDIAN | 739 | #if ATOM_BIG_ENDIAN |
678 | UCHAR ucReserved1:1; | 740 | UCHAR ucReserved1:1; |
679 | UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F | 741 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) |
680 | UCHAR ucReserved:3; | 742 | UCHAR ucReserved:3; |
681 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz | 743 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
682 | #else | 744 | #else |
683 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz | 745 | UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz |
684 | UCHAR ucReserved:3; | 746 | UCHAR ucReserved:3; |
685 | UCHAR ucDigSel:3; // =0: DIGA/B/C/D/E/F | 747 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) |
686 | UCHAR ucReserved1:1; | 748 | UCHAR ucReserved1:1; |
687 | #endif | 749 | #endif |
688 | }ATOM_DIG_ENCODER_CONFIG_V3; | 750 | }ATOM_DIG_ENCODER_CONFIG_V3; |
689 | 751 | ||
752 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 | ||
753 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 | ||
754 | #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 | ||
690 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 | 755 | #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 |
691 | 756 | #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 | |
757 | #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 | ||
758 | #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 | ||
759 | #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 | ||
760 | #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 | ||
761 | #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 | ||
692 | 762 | ||
693 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 | 763 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 |
694 | { | 764 | { |
@@ -707,6 +777,56 @@ typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 | |||
707 | UCHAR ucReserved; | 777 | UCHAR ucReserved; |
708 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; | 778 | }DIG_ENCODER_CONTROL_PARAMETERS_V3; |
709 | 779 | ||
780 | //ucTableFormatRevision=1 | ||
781 | //ucTableContentRevision=4 | ||
782 | // start from NI | ||
783 | // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver | ||
784 | typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 | ||
785 | { | ||
786 | #if ATOM_BIG_ENDIAN | ||
787 | UCHAR ucReserved1:1; | ||
788 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) | ||
789 | UCHAR ucReserved:2; | ||
790 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version | ||
791 | #else | ||
792 | UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version | ||
793 | UCHAR ucReserved:2; | ||
794 | UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also refered as DIGA/B/C/D/E/F) | ||
795 | UCHAR ucReserved1:1; | ||
796 | #endif | ||
797 | }ATOM_DIG_ENCODER_CONFIG_V4; | ||
798 | |||
799 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 | ||
800 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 | ||
801 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 | ||
802 | #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 | ||
803 | #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 | ||
804 | #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 | ||
805 | #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 | ||
806 | #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 | ||
807 | #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 | ||
808 | #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 | ||
809 | #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 | ||
810 | |||
811 | typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 | ||
812 | { | ||
813 | USHORT usPixelClock; // in 10KHz; for bios convenient | ||
814 | union{ | ||
815 | ATOM_DIG_ENCODER_CONFIG_V4 acConfig; | ||
816 | UCHAR ucConfig; | ||
817 | }; | ||
818 | UCHAR ucAction; | ||
819 | UCHAR ucEncoderMode; | ||
820 | // =0: DP encoder | ||
821 | // =1: LVDS encoder | ||
822 | // =2: DVI encoder | ||
823 | // =3: HDMI encoder | ||
824 | // =4: SDVO encoder | ||
825 | // =5: DP audio | ||
826 | UCHAR ucLaneNum; // how many lanes to enable | ||
827 | UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP | ||
828 | UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version | ||
829 | }DIG_ENCODER_CONTROL_PARAMETERS_V4; | ||
710 | 830 | ||
711 | // define ucBitPerColor: | 831 | // define ucBitPerColor: |
712 | #define PANEL_BPC_UNDEFINE 0x00 | 832 | #define PANEL_BPC_UNDEFINE 0x00 |
@@ -893,6 +1013,7 @@ typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 | |||
893 | #endif | 1013 | #endif |
894 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; | 1014 | }ATOM_DIG_TRANSMITTER_CONFIG_V3; |
895 | 1015 | ||
1016 | |||
896 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 | 1017 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 |
897 | { | 1018 | { |
898 | union | 1019 | union |
@@ -936,6 +1057,149 @@ typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 | |||
936 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD | 1057 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD |
937 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF | 1058 | #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF |
938 | 1059 | ||
1060 | |||
1061 | /****************************************************************************/ | ||
1062 | // Structures used by UNIPHYTransmitterControlTable V1.4 | ||
1063 | // ASIC Families: NI | ||
1064 | // ucTableFormatRevision=1 | ||
1065 | // ucTableContentRevision=4 | ||
1066 | /****************************************************************************/ | ||
1067 | typedef struct _ATOM_DP_VS_MODE_V4 | ||
1068 | { | ||
1069 | UCHAR ucLaneSel; | ||
1070 | union | ||
1071 | { | ||
1072 | UCHAR ucLaneSet; | ||
1073 | struct { | ||
1074 | #if ATOM_BIG_ENDIAN | ||
1075 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 | ||
1076 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level | ||
1077 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level | ||
1078 | #else | ||
1079 | UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level | ||
1080 | UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level | ||
1081 | UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 | ||
1082 | #endif | ||
1083 | }; | ||
1084 | }; | ||
1085 | }ATOM_DP_VS_MODE_V4; | ||
1086 | |||
1087 | typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 | ||
1088 | { | ||
1089 | #if ATOM_BIG_ENDIAN | ||
1090 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) | ||
1091 | // =1 Dig Transmitter 2 ( Uniphy CD ) | ||
1092 | // =2 Dig Transmitter 3 ( Uniphy EF ) | ||
1093 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New | ||
1094 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F | ||
1095 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E | ||
1096 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F | ||
1097 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) | ||
1098 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector | ||
1099 | #else | ||
1100 | UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector | ||
1101 | UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) | ||
1102 | UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E | ||
1103 | // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F | ||
1104 | UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F | ||
1105 | UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New | ||
1106 | UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) | ||
1107 | // =1 Dig Transmitter 2 ( Uniphy CD ) | ||
1108 | // =2 Dig Transmitter 3 ( Uniphy EF ) | ||
1109 | #endif | ||
1110 | }ATOM_DIG_TRANSMITTER_CONFIG_V4; | ||
1111 | |||
1112 | typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 | ||
1113 | { | ||
1114 | union | ||
1115 | { | ||
1116 | USHORT usPixelClock; // in 10KHz; for bios convenient | ||
1117 | USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h | ||
1118 | ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version | ||
1119 | }; | ||
1120 | union | ||
1121 | { | ||
1122 | ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; | ||
1123 | UCHAR ucConfig; | ||
1124 | }; | ||
1125 | UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX | ||
1126 | UCHAR ucLaneNum; | ||
1127 | UCHAR ucReserved[3]; | ||
1128 | }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; | ||
1129 | |||
1130 | //ucConfig | ||
1131 | //Bit0 | ||
1132 | #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 | ||
1133 | //Bit1 | ||
1134 | #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 | ||
1135 | //Bit2 | ||
1136 | #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 | ||
1137 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 | ||
1138 | #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 | ||
1139 | // Bit3 | ||
1140 | #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 | ||
1141 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 | ||
1142 | #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 | ||
1143 | // Bit5:4 | ||
1144 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 | ||
1145 | #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 | ||
1146 | #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 | ||
1147 | #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 | ||
1148 | #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 | ||
1149 | // Bit7:6 | ||
1150 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 | ||
1151 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB | ||
1152 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD | ||
1153 | #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF | ||
1154 | |||
1155 | |||
1156 | /****************************************************************************/ | ||
1157 | // Structures used by ExternalEncoderControlTable V1.3 | ||
1158 | // ASIC Families: Evergreen, Llano, NI | ||
1159 | // ucTableFormatRevision=1 | ||
1160 | // ucTableContentRevision=3 | ||
1161 | /****************************************************************************/ | ||
1162 | |||
1163 | typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 | ||
1164 | { | ||
1165 | union{ | ||
1166 | USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT | ||
1167 | USHORT usConnectorId; // connector id, valid when ucAction = INIT | ||
1168 | }; | ||
1169 | UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT | ||
1170 | UCHAR ucAction; // | ||
1171 | UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT | ||
1172 | UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT | ||
1173 | UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP | ||
1174 | UCHAR ucReserved; | ||
1175 | }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; | ||
1176 | |||
1177 | // ucAction | ||
1178 | #define EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 | ||
1179 | #define EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 | ||
1180 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 | ||
1181 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f | ||
1182 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 | ||
1183 | #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 | ||
1184 | #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 | ||
1185 | |||
1186 | // ucConfig | ||
1187 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 | ||
1188 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 | ||
1189 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 | ||
1190 | #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 | ||
1191 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MASK 0x70 | ||
1192 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 | ||
1193 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 | ||
1194 | #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 | ||
1195 | |||
1196 | typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 | ||
1197 | { | ||
1198 | EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; | ||
1199 | ULONG ulReserved[2]; | ||
1200 | }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; | ||
1201 | |||
1202 | |||
939 | /****************************************************************************/ | 1203 | /****************************************************************************/ |
940 | // Structures used by DAC1OuputControlTable | 1204 | // Structures used by DAC1OuputControlTable |
941 | // DAC2OuputControlTable | 1205 | // DAC2OuputControlTable |
@@ -1142,6 +1406,7 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V2 | |||
1142 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 | 1406 | #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 |
1143 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 | 1407 | #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 |
1144 | 1408 | ||
1409 | |||
1145 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 | 1410 | typedef struct _PIXEL_CLOCK_PARAMETERS_V3 |
1146 | { | 1411 | { |
1147 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) | 1412 | USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) |
@@ -1202,6 +1467,55 @@ typedef struct _PIXEL_CLOCK_PARAMETERS_V5 | |||
1202 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 | 1467 | #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 |
1203 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 | 1468 | #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 |
1204 | 1469 | ||
1470 | typedef struct _CRTC_PIXEL_CLOCK_FREQ | ||
1471 | { | ||
1472 | #if ATOM_BIG_ENDIAN | ||
1473 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to | ||
1474 | // drive the pixel clock. not used for DCPLL case. | ||
1475 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. | ||
1476 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. | ||
1477 | #else | ||
1478 | ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. | ||
1479 | // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. | ||
1480 | ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to | ||
1481 | // drive the pixel clock. not used for DCPLL case. | ||
1482 | #endif | ||
1483 | }CRTC_PIXEL_CLOCK_FREQ; | ||
1484 | |||
1485 | typedef struct _PIXEL_CLOCK_PARAMETERS_V6 | ||
1486 | { | ||
1487 | union{ | ||
1488 | CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency | ||
1489 | ULONG ulDispEngClkFreq; // dispclk frequency | ||
1490 | }; | ||
1491 | USHORT usFbDiv; // feedback divider integer part. | ||
1492 | UCHAR ucPostDiv; // post divider. | ||
1493 | UCHAR ucRefDiv; // Reference divider | ||
1494 | UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL | ||
1495 | UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, | ||
1496 | // indicate which graphic encoder will be used. | ||
1497 | UCHAR ucEncoderMode; // Encoder mode: | ||
1498 | UCHAR ucMiscInfo; // bit[0]= Force program PPLL | ||
1499 | // bit[1]= when VGA timing is used. | ||
1500 | // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp | ||
1501 | // bit[4]= RefClock source for PPLL. | ||
1502 | // =0: XTLAIN( default mode ) | ||
1503 | // =1: other external clock source, which is pre-defined | ||
1504 | // by VBIOS depend on the feature required. | ||
1505 | // bit[7:5]: reserved. | ||
1506 | ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) | ||
1507 | |||
1508 | }PIXEL_CLOCK_PARAMETERS_V6; | ||
1509 | |||
1510 | #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 | ||
1511 | #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 | ||
1512 | #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c | ||
1513 | #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 | ||
1514 | #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 | ||
1515 | #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 | ||
1516 | #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c | ||
1517 | #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 | ||
1518 | |||
1205 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 | 1519 | typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 |
1206 | { | 1520 | { |
1207 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; | 1521 | PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; |
@@ -1241,10 +1555,11 @@ typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS | |||
1241 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 | 1555 | typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 |
1242 | { | 1556 | { |
1243 | USHORT usPixelClock; // target pixel clock | 1557 | USHORT usPixelClock; // target pixel clock |
1244 | UCHAR ucTransmitterID; // transmitter id defined in objectid.h | 1558 | UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h |
1245 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI | 1559 | UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI |
1246 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX | 1560 | UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX |
1247 | UCHAR ucReserved[3]; | 1561 | UCHAR ucExtTransmitterID; // external encoder id. |
1562 | UCHAR ucReserved[2]; | ||
1248 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; | 1563 | }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; |
1249 | 1564 | ||
1250 | // usDispPllConfig v1.2 for RoadRunner | 1565 | // usDispPllConfig v1.2 for RoadRunner |
@@ -1358,6 +1673,7 @@ typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS | |||
1358 | /**************************************************************************/ | 1673 | /**************************************************************************/ |
1359 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS | 1674 | #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
1360 | 1675 | ||
1676 | |||
1361 | /****************************************************************************/ | 1677 | /****************************************************************************/ |
1362 | // Structures used by PowerConnectorDetectionTable | 1678 | // Structures used by PowerConnectorDetectionTable |
1363 | /****************************************************************************/ | 1679 | /****************************************************************************/ |
@@ -1438,6 +1754,31 @@ typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 | |||
1438 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 | 1754 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 |
1439 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 | 1755 | #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 |
1440 | 1756 | ||
1757 | // Used by DCE5.0 | ||
1758 | typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 | ||
1759 | { | ||
1760 | USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 | ||
1761 | UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. | ||
1762 | // Bit[1]: 1-Ext. 0-Int. | ||
1763 | // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL | ||
1764 | // Bits[7:4] reserved | ||
1765 | UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE | ||
1766 | USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] | ||
1767 | USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC | ||
1768 | }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; | ||
1769 | |||
1770 | #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 | ||
1771 | #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 | ||
1772 | #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 | ||
1773 | #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c | ||
1774 | #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 | ||
1775 | #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 | ||
1776 | #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 | ||
1777 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF | ||
1778 | #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 | ||
1779 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 | ||
1780 | #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 | ||
1781 | |||
1441 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL | 1782 | #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL |
1442 | 1783 | ||
1443 | /**************************************************************************/ | 1784 | /**************************************************************************/ |
@@ -1706,7 +2047,7 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES | |||
1706 | USHORT StandardVESA_Timing; // Only used by Bios | 2047 | USHORT StandardVESA_Timing; // Only used by Bios |
1707 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 | 2048 | USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 |
1708 | USHORT DAC_Info; // Will be obsolete from R600 | 2049 | USHORT DAC_Info; // Will be obsolete from R600 |
1709 | USHORT LVDS_Info; // Shared by various SW components,latest version 1.1 | 2050 | USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info |
1710 | USHORT TMDS_Info; // Will be obsolete from R600 | 2051 | USHORT TMDS_Info; // Will be obsolete from R600 |
1711 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 | 2052 | USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 |
1712 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 | 2053 | USHORT SupportedDevicesInfo; // Will be obsolete from R600 |
@@ -1736,12 +2077,16 @@ typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES | |||
1736 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 | 2077 | USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 |
1737 | }ATOM_MASTER_LIST_OF_DATA_TABLES; | 2078 | }ATOM_MASTER_LIST_OF_DATA_TABLES; |
1738 | 2079 | ||
2080 | // For backward compatible | ||
2081 | #define LVDS_Info LCD_Info | ||
2082 | |||
1739 | typedef struct _ATOM_MASTER_DATA_TABLE | 2083 | typedef struct _ATOM_MASTER_DATA_TABLE |
1740 | { | 2084 | { |
1741 | ATOM_COMMON_TABLE_HEADER sHeader; | 2085 | ATOM_COMMON_TABLE_HEADER sHeader; |
1742 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; | 2086 | ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; |
1743 | }ATOM_MASTER_DATA_TABLE; | 2087 | }ATOM_MASTER_DATA_TABLE; |
1744 | 2088 | ||
2089 | |||
1745 | /****************************************************************************/ | 2090 | /****************************************************************************/ |
1746 | // Structure used in MultimediaCapabilityInfoTable | 2091 | // Structure used in MultimediaCapabilityInfoTable |
1747 | /****************************************************************************/ | 2092 | /****************************************************************************/ |
@@ -1776,6 +2121,7 @@ typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO | |||
1776 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) | 2121 | UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) |
1777 | }ATOM_MULTIMEDIA_CONFIG_INFO; | 2122 | }ATOM_MULTIMEDIA_CONFIG_INFO; |
1778 | 2123 | ||
2124 | |||
1779 | /****************************************************************************/ | 2125 | /****************************************************************************/ |
1780 | // Structures used in FirmwareInfoTable | 2126 | // Structures used in FirmwareInfoTable |
1781 | /****************************************************************************/ | 2127 | /****************************************************************************/ |
@@ -2031,8 +2377,47 @@ typedef struct _ATOM_FIRMWARE_INFO_V2_1 | |||
2031 | UCHAR ucReserved4[3]; | 2377 | UCHAR ucReserved4[3]; |
2032 | }ATOM_FIRMWARE_INFO_V2_1; | 2378 | }ATOM_FIRMWARE_INFO_V2_1; |
2033 | 2379 | ||
2380 | //the structure below to be used from NI | ||
2381 | //ucTableFormatRevision=2 | ||
2382 | //ucTableContentRevision=2 | ||
2383 | typedef struct _ATOM_FIRMWARE_INFO_V2_2 | ||
2384 | { | ||
2385 | ATOM_COMMON_TABLE_HEADER sHeader; | ||
2386 | ULONG ulFirmwareRevision; | ||
2387 | ULONG ulDefaultEngineClock; //In 10Khz unit | ||
2388 | ULONG ulDefaultMemoryClock; //In 10Khz unit | ||
2389 | ULONG ulReserved[2]; | ||
2390 | ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* | ||
2391 | ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* | ||
2392 | ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit | ||
2393 | ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? | ||
2394 | ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. | ||
2395 | UCHAR ucReserved3; //Was ucASICMaxTemperature; | ||
2396 | UCHAR ucMinAllowedBL_Level; | ||
2397 | USHORT usBootUpVDDCVoltage; //In MV unit | ||
2398 | USHORT usLcdMinPixelClockPLL_Output; // In MHz unit | ||
2399 | USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit | ||
2400 | ULONG ulReserved4; //Was ulAsicMaximumVoltage | ||
2401 | ULONG ulMinPixelClockPLL_Output; //In 10Khz unit | ||
2402 | ULONG ulReserved5; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input | ||
2403 | ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input | ||
2404 | ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output | ||
2405 | USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC | ||
2406 | USHORT usMinPixelClockPLL_Input; //In 10Khz unit | ||
2407 | USHORT usMaxPixelClockPLL_Input; //In 10Khz unit | ||
2408 | USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; | ||
2409 | ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; | ||
2410 | USHORT usCoreReferenceClock; //In 10Khz unit | ||
2411 | USHORT usMemoryReferenceClock; //In 10Khz unit | ||
2412 | USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock | ||
2413 | UCHAR ucMemoryModule_ID; //Indicate what is the board design | ||
2414 | UCHAR ucReserved9[3]; | ||
2415 | USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; | ||
2416 | USHORT usReserved12; | ||
2417 | ULONG ulReserved10[3]; // New added comparing to previous version | ||
2418 | }ATOM_FIRMWARE_INFO_V2_2; | ||
2034 | 2419 | ||
2035 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_1 | 2420 | #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 |
2036 | 2421 | ||
2037 | /****************************************************************************/ | 2422 | /****************************************************************************/ |
2038 | // Structures used in IntegratedSystemInfoTable | 2423 | // Structures used in IntegratedSystemInfoTable |
@@ -2212,7 +2597,7 @@ ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pi | |||
2212 | ucDockingPinBit: which bit in this register to read the pin status; | 2597 | ucDockingPinBit: which bit in this register to read the pin status; |
2213 | ucDockingPinPolarity:Polarity of the pin when docked; | 2598 | ucDockingPinPolarity:Polarity of the pin when docked; |
2214 | 2599 | ||
2215 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, other bits reserved for now and must be 0x0 | 2600 | ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 |
2216 | 2601 | ||
2217 | usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. | 2602 | usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. |
2218 | 2603 | ||
@@ -2250,6 +2635,14 @@ usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to rep | |||
2250 | usMinDownStreamHTLinkWidth: same as above. | 2635 | usMinDownStreamHTLinkWidth: same as above. |
2251 | */ | 2636 | */ |
2252 | 2637 | ||
2638 | // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition | ||
2639 | #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 | ||
2640 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 | ||
2641 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 | ||
2642 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 | ||
2643 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 | ||
2644 | |||
2645 | #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH // this deff reflects max defined CPU code | ||
2253 | 2646 | ||
2254 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 | 2647 | #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 |
2255 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 | 2648 | #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 |
@@ -2778,8 +3171,88 @@ typedef struct _ATOM_LVDS_INFO_V12 | |||
2778 | #define PANEL_RANDOM_DITHER 0x80 | 3171 | #define PANEL_RANDOM_DITHER 0x80 |
2779 | #define PANEL_RANDOM_DITHER_MASK 0x80 | 3172 | #define PANEL_RANDOM_DITHER_MASK 0x80 |
2780 | 3173 | ||
3174 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this | ||
3175 | |||
3176 | /****************************************************************************/ | ||
3177 | // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 | ||
3178 | // ASIC Families: NI | ||
3179 | // ucTableFormatRevision=1 | ||
3180 | // ucTableContentRevision=3 | ||
3181 | /****************************************************************************/ | ||
3182 | typedef struct _ATOM_LCD_INFO_V13 | ||
3183 | { | ||
3184 | ATOM_COMMON_TABLE_HEADER sHeader; | ||
3185 | ATOM_DTD_FORMAT sLCDTiming; | ||
3186 | USHORT usExtInfoTableOffset; | ||
3187 | USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. | ||
3188 | ULONG ulReserved0; | ||
3189 | UCHAR ucLCD_Misc; // Reorganized in V13 | ||
3190 | // Bit0: {=0:single, =1:dual}, | ||
3191 | // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, | ||
3192 | // Bit3:2: {Grey level} | ||
3193 | // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) | ||
3194 | // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? | ||
3195 | UCHAR ucPanelDefaultRefreshRate; | ||
3196 | UCHAR ucPanelIdentification; | ||
3197 | UCHAR ucSS_Id; | ||
3198 | USHORT usLCDVenderID; | ||
3199 | USHORT usLCDProductID; | ||
3200 | UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 | ||
3201 | // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own | ||
3202 | // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED | ||
3203 | // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) | ||
3204 | // Bit7-3: Reserved | ||
3205 | UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable | ||
3206 | USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 | ||
3207 | |||
3208 | UCHAR ucPowerSequenceDIGONtoDE_in4Ms; | ||
3209 | UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; | ||
3210 | UCHAR ucPowerSequenceDEtoDIGON_in4Ms; | ||
3211 | UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; | ||
3212 | |||
3213 | UCHAR ucOffDelay_in4Ms; | ||
3214 | UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; | ||
3215 | UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; | ||
3216 | UCHAR ucReserved1; | ||
3217 | |||
3218 | ULONG ulReserved[4]; | ||
3219 | }ATOM_LCD_INFO_V13; | ||
3220 | |||
3221 | #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 | ||
3222 | |||
3223 | //Definitions for ucLCD_Misc | ||
3224 | #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 | ||
3225 | #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 | ||
3226 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C | ||
3227 | #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 | ||
3228 | #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 | ||
3229 | #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 | ||
3230 | #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 | ||
3231 | |||
3232 | //Color Bit Depth definition in EDID V1.4 @BYTE 14h | ||
3233 | //Bit 6 5 4 | ||
3234 | // 0 0 0 - Color bit depth is undefined | ||
3235 | // 0 0 1 - 6 Bits per Primary Color | ||
3236 | // 0 1 0 - 8 Bits per Primary Color | ||
3237 | // 0 1 1 - 10 Bits per Primary Color | ||
3238 | // 1 0 0 - 12 Bits per Primary Color | ||
3239 | // 1 0 1 - 14 Bits per Primary Color | ||
3240 | // 1 1 0 - 16 Bits per Primary Color | ||
3241 | // 1 1 1 - Reserved | ||
3242 | |||
3243 | //Definitions for ucLCDPanel_SpecialHandlingCap: | ||
3244 | |||
3245 | //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. | ||
3246 | //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL | ||
3247 | #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version | ||
2781 | 3248 | ||
2782 | #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 | 3249 | //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together |
3250 | //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static | ||
3251 | //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 | ||
3252 | #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version | ||
3253 | |||
3254 | //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. | ||
3255 | #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version | ||
2783 | 3256 | ||
2784 | typedef struct _ATOM_PATCH_RECORD_MODE | 3257 | typedef struct _ATOM_PATCH_RECORD_MODE |
2785 | { | 3258 | { |
@@ -2944,9 +3417,9 @@ typedef struct _ATOM_DPCD_INFO | |||
2944 | #define MAX_DTD_MODE_IN_VRAM 6 | 3417 | #define MAX_DTD_MODE_IN_VRAM 6 |
2945 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) | 3418 | #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) |
2946 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) | 3419 | #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) |
2947 | #define DFP_ENCODER_TYPE_OFFSET 0x80 | 3420 | //20 bytes for Encoder Type and DPCD in STD EDID area |
2948 | #define DP_ENCODER_LANE_NUM_OFFSET 0x84 | 3421 | #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) |
2949 | #define DP_ENCODER_LINK_RATE_OFFSET 0x88 | 3422 | #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) |
2950 | 3423 | ||
2951 | #define ATOM_HWICON1_SURFACE_ADDR 0 | 3424 | #define ATOM_HWICON1_SURFACE_ADDR 0 |
2952 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) | 3425 | #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) |
@@ -2997,14 +3470,16 @@ typedef struct _ATOM_DPCD_INFO | |||
2997 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) | 3470 | #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) |
2998 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) | 3471 | #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) |
2999 | 3472 | ||
3000 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR+ATOM_STD_MODE_SUPPORT_TBL_SIZE) | 3473 | #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) |
3001 | 3474 | ||
3002 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR+256) | 3475 | #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) |
3003 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START+512 | 3476 | #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 |
3004 | 3477 | ||
3005 | //The size below is in Kb! | 3478 | //The size below is in Kb! |
3006 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) | 3479 | #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) |
3007 | 3480 | ||
3481 | #define ATOM_VRAM_RESERVE_V2_SIZE 32 | ||
3482 | |||
3008 | #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L | 3483 | #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L |
3009 | #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 | 3484 | #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 |
3010 | #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 | 3485 | #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 |
@@ -3206,6 +3681,15 @@ typedef struct _ATOM_DISPLAY_OBJECT_PATH | |||
3206 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. | 3681 | USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. |
3207 | }ATOM_DISPLAY_OBJECT_PATH; | 3682 | }ATOM_DISPLAY_OBJECT_PATH; |
3208 | 3683 | ||
3684 | typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH | ||
3685 | { | ||
3686 | USHORT usDeviceTag; //supported device | ||
3687 | USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH | ||
3688 | USHORT usConnObjectId; //Connector Object ID | ||
3689 | USHORT usGPUObjectId; //GPU ID | ||
3690 | USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder | ||
3691 | }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; | ||
3692 | |||
3209 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE | 3693 | typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE |
3210 | { | 3694 | { |
3211 | UCHAR ucNumOfDispPath; | 3695 | UCHAR ucNumOfDispPath; |
@@ -3261,6 +3745,47 @@ typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset | |||
3261 | #define EXT_AUXDDC_LUTINDEX_7 7 | 3745 | #define EXT_AUXDDC_LUTINDEX_7 7 |
3262 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) | 3746 | #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) |
3263 | 3747 | ||
3748 | //ucChannelMapping are defined as following | ||
3749 | //for DP connector, eDP, DP to VGA/LVDS | ||
3750 | //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3751 | //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3752 | //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3753 | //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3754 | typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING | ||
3755 | { | ||
3756 | #if ATOM_BIG_ENDIAN | ||
3757 | UCHAR ucDP_Lane3_Source:2; | ||
3758 | UCHAR ucDP_Lane2_Source:2; | ||
3759 | UCHAR ucDP_Lane1_Source:2; | ||
3760 | UCHAR ucDP_Lane0_Source:2; | ||
3761 | #else | ||
3762 | UCHAR ucDP_Lane0_Source:2; | ||
3763 | UCHAR ucDP_Lane1_Source:2; | ||
3764 | UCHAR ucDP_Lane2_Source:2; | ||
3765 | UCHAR ucDP_Lane3_Source:2; | ||
3766 | #endif | ||
3767 | }ATOM_DP_CONN_CHANNEL_MAPPING; | ||
3768 | |||
3769 | //for DVI/HDMI, in dual link case, both links have to have same mapping. | ||
3770 | //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3771 | //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3772 | //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3773 | //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 | ||
3774 | typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING | ||
3775 | { | ||
3776 | #if ATOM_BIG_ENDIAN | ||
3777 | UCHAR ucDVI_CLK_Source:2; | ||
3778 | UCHAR ucDVI_DATA0_Source:2; | ||
3779 | UCHAR ucDVI_DATA1_Source:2; | ||
3780 | UCHAR ucDVI_DATA2_Source:2; | ||
3781 | #else | ||
3782 | UCHAR ucDVI_DATA2_Source:2; | ||
3783 | UCHAR ucDVI_DATA1_Source:2; | ||
3784 | UCHAR ucDVI_DATA0_Source:2; | ||
3785 | UCHAR ucDVI_CLK_Source:2; | ||
3786 | #endif | ||
3787 | }ATOM_DVI_CONN_CHANNEL_MAPPING; | ||
3788 | |||
3264 | typedef struct _EXT_DISPLAY_PATH | 3789 | typedef struct _EXT_DISPLAY_PATH |
3265 | { | 3790 | { |
3266 | USHORT usDeviceTag; //A bit vector to show what devices are supported | 3791 | USHORT usDeviceTag; //A bit vector to show what devices are supported |
@@ -3269,7 +3794,13 @@ typedef struct _EXT_DISPLAY_PATH | |||
3269 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT | 3794 | UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT |
3270 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT | 3795 | UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT |
3271 | USHORT usExtEncoderObjId; //external encoder object id | 3796 | USHORT usExtEncoderObjId; //external encoder object id |
3272 | USHORT usReserved[3]; | 3797 | union{ |
3798 | UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping | ||
3799 | ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; | ||
3800 | ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; | ||
3801 | }; | ||
3802 | UCHAR ucReserved; | ||
3803 | USHORT usReserved[2]; | ||
3273 | }EXT_DISPLAY_PATH; | 3804 | }EXT_DISPLAY_PATH; |
3274 | 3805 | ||
3275 | #define NUMBER_OF_UCHAR_FOR_GUID 16 | 3806 | #define NUMBER_OF_UCHAR_FOR_GUID 16 |
@@ -3281,7 +3812,8 @@ typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO | |||
3281 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string | 3812 | UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string |
3282 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. | 3813 | EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. |
3283 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. | 3814 | UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. |
3284 | UCHAR Reserved [7]; // for potential expansion | 3815 | UCHAR uc3DStereoPinId; // use for eDP panel |
3816 | UCHAR Reserved [6]; // for potential expansion | ||
3285 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; | 3817 | }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; |
3286 | 3818 | ||
3287 | //Related definitions, all records are differnt but they have a commond header | 3819 | //Related definitions, all records are differnt but they have a commond header |
@@ -3311,10 +3843,11 @@ typedef struct _ATOM_COMMON_RECORD_HEADER | |||
3311 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table | 3843 | #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table |
3312 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record | 3844 | #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record |
3313 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 | 3845 | #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 |
3846 | #define ATOM_ENCODER_CAP_RECORD_TYPE 20 | ||
3314 | 3847 | ||
3315 | 3848 | ||
3316 | //Must be updated when new record type is added,equal to that record definition! | 3849 | //Must be updated when new record type is added,equal to that record definition! |
3317 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE | 3850 | #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE |
3318 | 3851 | ||
3319 | typedef struct _ATOM_I2C_RECORD | 3852 | typedef struct _ATOM_I2C_RECORD |
3320 | { | 3853 | { |
@@ -3441,6 +3974,26 @@ typedef struct _ATOM_ENCODER_DVO_CF_RECORD | |||
3441 | UCHAR ucPadding[2]; | 3974 | UCHAR ucPadding[2]; |
3442 | }ATOM_ENCODER_DVO_CF_RECORD; | 3975 | }ATOM_ENCODER_DVO_CF_RECORD; |
3443 | 3976 | ||
3977 | // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap | ||
3978 | #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by this path | ||
3979 | |||
3980 | typedef struct _ATOM_ENCODER_CAP_RECORD | ||
3981 | { | ||
3982 | ATOM_COMMON_RECORD_HEADER sheader; | ||
3983 | union { | ||
3984 | USHORT usEncoderCap; | ||
3985 | struct { | ||
3986 | #if ATOM_BIG_ENDIAN | ||
3987 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future | ||
3988 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. | ||
3989 | #else | ||
3990 | USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. | ||
3991 | USHORT usReserved:15; // Bit1-15 may be defined for other capability in future | ||
3992 | #endif | ||
3993 | }; | ||
3994 | }; | ||
3995 | }ATOM_ENCODER_CAP_RECORD; | ||
3996 | |||
3444 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle | 3997 | // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle |
3445 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 | 3998 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 |
3446 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 | 3999 | #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 |
@@ -3580,6 +4133,11 @@ typedef struct _ATOM_VOLTAGE_CONTROL | |||
3580 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI | 4133 | #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI |
3581 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage | 4134 | #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage |
3582 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 | 4135 | #define VOLTAGE_CONTROL_ID_DS4402 0x04 |
4136 | #define VOLTAGE_CONTROL_ID_UP6266 0x05 | ||
4137 | #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 | ||
4138 | #define VOLTAGE_CONTROL_ID_VT1556M 0x07 | ||
4139 | #define VOLTAGE_CONTROL_ID_CHL822x 0x08 | ||
4140 | #define VOLTAGE_CONTROL_ID_VT1586M 0x09 | ||
3583 | 4141 | ||
3584 | typedef struct _ATOM_VOLTAGE_OBJECT | 4142 | typedef struct _ATOM_VOLTAGE_OBJECT |
3585 | { | 4143 | { |
@@ -3670,66 +4228,157 @@ typedef struct _ATOM_POWER_SOURCE_INFO | |||
3670 | #define POWER_SENSOR_GPIO 0x01 | 4228 | #define POWER_SENSOR_GPIO 0x01 |
3671 | #define POWER_SENSOR_I2C 0x02 | 4229 | #define POWER_SENSOR_I2C 0x02 |
3672 | 4230 | ||
4231 | typedef struct _ATOM_CLK_VOLT_CAPABILITY | ||
4232 | { | ||
4233 | ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table | ||
4234 | ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz | ||
4235 | }ATOM_CLK_VOLT_CAPABILITY; | ||
4236 | |||
4237 | typedef struct _ATOM_AVAILABLE_SCLK_LIST | ||
4238 | { | ||
4239 | ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz | ||
4240 | USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK | ||
4241 | USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK | ||
4242 | }ATOM_AVAILABLE_SCLK_LIST; | ||
4243 | |||
4244 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition | ||
4245 | #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] | ||
4246 | |||
4247 | // this IntegrateSystemInfoTable is used for Liano/Ontario APU | ||
3673 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 | 4248 | typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 |
3674 | { | 4249 | { |
3675 | ATOM_COMMON_TABLE_HEADER sHeader; | 4250 | ATOM_COMMON_TABLE_HEADER sHeader; |
3676 | ULONG ulBootUpEngineClock; | 4251 | ULONG ulBootUpEngineClock; |
3677 | ULONG ulDentistVCOFreq; | 4252 | ULONG ulDentistVCOFreq; |
3678 | ULONG ulBootUpUMAClock; | 4253 | ULONG ulBootUpUMAClock; |
3679 | ULONG ulReserved1[8]; | 4254 | ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; |
3680 | ULONG ulBootUpReqDisplayVector; | 4255 | ULONG ulBootUpReqDisplayVector; |
3681 | ULONG ulOtherDisplayMisc; | 4256 | ULONG ulOtherDisplayMisc; |
3682 | ULONG ulGPUCapInfo; | 4257 | ULONG ulGPUCapInfo; |
3683 | ULONG ulReserved2[3]; | 4258 | ULONG ulSB_MMIO_Base_Addr; |
4259 | USHORT usRequestedPWMFreqInHz; | ||
4260 | UCHAR ucHtcTmpLmt; | ||
4261 | UCHAR ucHtcHystLmt; | ||
4262 | ULONG ulMinEngineClock; | ||
3684 | ULONG ulSystemConfig; | 4263 | ULONG ulSystemConfig; |
3685 | ULONG ulCPUCapInfo; | 4264 | ULONG ulCPUCapInfo; |
3686 | USHORT usMaxNBVoltage; | 4265 | USHORT usNBP0Voltage; |
3687 | USHORT usMinNBVoltage; | 4266 | USHORT usNBP1Voltage; |
3688 | USHORT usBootUpNBVoltage; | 4267 | USHORT usBootUpNBVoltage; |
3689 | USHORT usExtDispConnInfoOffset; | 4268 | USHORT usExtDispConnInfoOffset; |
3690 | UCHAR ucHtcTmpLmt; | 4269 | USHORT usPanelRefreshRateRange; |
3691 | UCHAR ucTjOffset; | ||
3692 | UCHAR ucMemoryType; | 4270 | UCHAR ucMemoryType; |
3693 | UCHAR ucUMAChannelNumber; | 4271 | UCHAR ucUMAChannelNumber; |
3694 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; | 4272 | ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; |
3695 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; | 4273 | ULONG ulCSR_M3_ARB_CNTL_UVD[10]; |
3696 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; | 4274 | ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; |
3697 | ULONG ulReserved3[42]; | 4275 | ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; |
4276 | ULONG ulGMCRestoreResetTime; | ||
4277 | ULONG ulMinimumNClk; | ||
4278 | ULONG ulIdleNClk; | ||
4279 | ULONG ulDDR_DLL_PowerUpTime; | ||
4280 | ULONG ulDDR_PLL_PowerUpTime; | ||
4281 | USHORT usPCIEClkSSPercentage; | ||
4282 | USHORT usPCIEClkSSType; | ||
4283 | USHORT usLvdsSSPercentage; | ||
4284 | USHORT usLvdsSSpreadRateIn10Hz; | ||
4285 | USHORT usHDMISSPercentage; | ||
4286 | USHORT usHDMISSpreadRateIn10Hz; | ||
4287 | USHORT usDVISSPercentage; | ||
4288 | USHORT usDVISSpreadRateIn10Hz; | ||
4289 | ULONG ulReserved3[21]; | ||
3698 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; | 4290 | ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; |
3699 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; | 4291 | }ATOM_INTEGRATED_SYSTEM_INFO_V6; |
3700 | 4292 | ||
4293 | // ulGPUCapInfo | ||
4294 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 | ||
4295 | #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 | ||
4296 | |||
4297 | // ulOtherDisplayMisc | ||
4298 | #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 | ||
4299 | |||
4300 | |||
3701 | /********************************************************************************************************************** | 4301 | /********************************************************************************************************************** |
3702 | // ATOM_INTEGRATED_SYSTEM_INFO_V6 Description | 4302 | ATOM_INTEGRATED_SYSTEM_INFO_V6 Description |
3703 | //ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. | 4303 | ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock |
3704 | //ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. | 4304 | ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. |
3705 | //ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. | 4305 | ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. |
3706 | //ulReserved1[8] Reserved by now, must be 0x0. | 4306 | sDISPCLK_Voltage: Report Display clock voltage requirement. |
3707 | //ulBootUpReqDisplayVector VBIOS boot up display IDs | 4307 | |
3708 | // ATOM_DEVICE_CRT1_SUPPORT 0x0001 | 4308 | ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: |
3709 | // ATOM_DEVICE_CRT2_SUPPORT 0x0010 | 4309 | ATOM_DEVICE_CRT1_SUPPORT 0x0001 |
3710 | // ATOM_DEVICE_DFP1_SUPPORT 0x0008 | 4310 | ATOM_DEVICE_CRT2_SUPPORT 0x0010 |
3711 | // ATOM_DEVICE_DFP6_SUPPORT 0x0040 | 4311 | ATOM_DEVICE_DFP1_SUPPORT 0x0008 |
3712 | // ATOM_DEVICE_DFP2_SUPPORT 0x0080 | 4312 | ATOM_DEVICE_DFP6_SUPPORT 0x0040 |
3713 | // ATOM_DEVICE_DFP3_SUPPORT 0x0200 | 4313 | ATOM_DEVICE_DFP2_SUPPORT 0x0080 |
3714 | // ATOM_DEVICE_DFP4_SUPPORT 0x0400 | 4314 | ATOM_DEVICE_DFP3_SUPPORT 0x0200 |
3715 | // ATOM_DEVICE_DFP5_SUPPORT 0x0800 | 4315 | ATOM_DEVICE_DFP4_SUPPORT 0x0400 |
3716 | // ATOM_DEVICE_LCD1_SUPPORT 0x0002 | 4316 | ATOM_DEVICE_DFP5_SUPPORT 0x0800 |
3717 | //ulOtherDisplayMisc Other display related flags, not defined yet. | 4317 | ATOM_DEVICE_LCD1_SUPPORT 0x0002 |
3718 | //ulGPUCapInfo TBD | 4318 | ulOtherDisplayMisc: Other display related flags, not defined yet. |
3719 | //ulReserved2[3] must be 0x0 for the reserved. | 4319 | ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. |
3720 | //ulSystemConfig TBD | 4320 | =1: TMDS/HDMI Coherent Mode use signel PLL mode. |
3721 | //ulCPUCapInfo TBD | 4321 | bit[3]=0: Enable HW AUX mode detection logic |
3722 | //usMaxNBVoltage High NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. | 4322 | =1: Disable HW AUX mode dettion logic |
3723 | //usMinNBVoltage Low NB voltage in unit of mv, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse. | 4323 | ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. |
3724 | //usBootUpNBVoltage Boot up NB voltage in unit of mv. | 4324 | |
3725 | //ucHtcTmpLmt Bit [22:16] of D24F3x64 Thermal Control (HTC) Register. | 4325 | usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). |
3726 | //ucTjOffset Bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed. | 4326 | Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; |
3727 | //ucMemoryType [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. | 4327 | |
3728 | //ucUMAChannelNumber System memory channel numbers. | 4328 | When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: |
3729 | //usExtDispConnectionInfoOffset ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO offset relative to beginning of this table. | 4329 | 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; |
3730 | //ulCSR_M3_ARB_CNTL_DEFAULT[10] Arrays with values for CSR M3 arbiter for default | 4330 | VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, |
3731 | //ulCSR_M3_ARB_CNTL_UVD[10] Arrays with values for CSR M3 arbiter for UVD playback. | 4331 | Changing BL using VBIOS function is functional in both driver and non-driver present environment; |
3732 | //ulCSR_M3_ARB_CNTL_FS3D[10] Arrays with values for CSR M3 arbiter for Full Screen 3D applications. | 4332 | and enabling VariBri under the driver environment from PP table is optional. |
4333 | |||
4334 | 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating | ||
4335 | that BL control from GPU is expected. | ||
4336 | VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 | ||
4337 | Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but | ||
4338 | it's per platform | ||
4339 | and enabling VariBri under the driver environment from PP table is optional. | ||
4340 | |||
4341 | ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. | ||
4342 | Threshold on value to enter HTC_active state. | ||
4343 | ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. | ||
4344 | To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. | ||
4345 | ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. | ||
4346 | ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled | ||
4347 | =1: PCIE Power Gating Enabled | ||
4348 | Bit[1]=0: DDR-DLL shut-down feature disabled. | ||
4349 | 1: DDR-DLL shut-down feature enabled. | ||
4350 | Bit[2]=0: DDR-PLL Power down feature disabled. | ||
4351 | 1: DDR-PLL Power down feature enabled. | ||
4352 | ulCPUCapInfo: TBD | ||
4353 | usNBP0Voltage: VID for voltage on NB P0 State | ||
4354 | usNBP1Voltage: VID for voltage on NB P1 State | ||
4355 | usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. | ||
4356 | usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure | ||
4357 | usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set | ||
4358 | to indicate a range. | ||
4359 | SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 | ||
4360 | SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 | ||
4361 | SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 | ||
4362 | SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 | ||
4363 | ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. | ||
4364 | ucUMAChannelNumber: System memory channel numbers. | ||
4365 | ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default | ||
4366 | ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. | ||
4367 | ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. | ||
4368 | sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high | ||
4369 | ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. | ||
4370 | ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. | ||
4371 | ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. | ||
4372 | ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. | ||
4373 | ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. | ||
4374 | usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. | ||
4375 | usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. | ||
4376 | usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. | ||
4377 | usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. | ||
4378 | usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. | ||
4379 | usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. | ||
4380 | usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. | ||
4381 | usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. | ||
3733 | **********************************************************************************************************************/ | 4382 | **********************************************************************************************************************/ |
3734 | 4383 | ||
3735 | /**************************************************************************/ | 4384 | /**************************************************************************/ |
@@ -3790,6 +4439,7 @@ typedef struct _ATOM_ASIC_SS_ASSIGNMENT | |||
3790 | #define ASIC_INTERNAL_SS_ON_LVDS 6 | 4439 | #define ASIC_INTERNAL_SS_ON_LVDS 6 |
3791 | #define ASIC_INTERNAL_SS_ON_DP 7 | 4440 | #define ASIC_INTERNAL_SS_ON_DP 7 |
3792 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 | 4441 | #define ASIC_INTERNAL_SS_ON_DCPLL 8 |
4442 | #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 | ||
3793 | 4443 | ||
3794 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 | 4444 | typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 |
3795 | { | 4445 | { |
@@ -3903,6 +4553,7 @@ typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 | |||
3903 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 | 4553 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 |
3904 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 | 4554 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 |
3905 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 | 4555 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 |
4556 | #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 | ||
3906 | 4557 | ||
3907 | //Byte aligned defintion for BIOS usage | 4558 | //Byte aligned defintion for BIOS usage |
3908 | #define ATOM_S0_CRT1_MONOb0 0x01 | 4559 | #define ATOM_S0_CRT1_MONOb0 0x01 |
@@ -4529,7 +5180,8 @@ typedef struct _ATOM_INIT_REG_BLOCK{ | |||
4529 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) | 5180 | #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) |
4530 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) | 5181 | #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) |
4531 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) | 5182 | #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) |
4532 | 5183 | //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code | |
5184 | #define ACCESS_PLACEHOLDER 0x80 | ||
4533 | 5185 | ||
4534 | typedef struct _ATOM_MC_INIT_PARAM_TABLE | 5186 | typedef struct _ATOM_MC_INIT_PARAM_TABLE |
4535 | { | 5187 | { |
@@ -4554,6 +5206,10 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE | |||
4554 | #define _32Mx32 0x33 | 5206 | #define _32Mx32 0x33 |
4555 | #define _64Mx8 0x41 | 5207 | #define _64Mx8 0x41 |
4556 | #define _64Mx16 0x42 | 5208 | #define _64Mx16 0x42 |
5209 | #define _64Mx32 0x43 | ||
5210 | #define _128Mx8 0x51 | ||
5211 | #define _128Mx16 0x52 | ||
5212 | #define _256Mx8 0x61 | ||
4557 | 5213 | ||
4558 | #define SAMSUNG 0x1 | 5214 | #define SAMSUNG 0x1 |
4559 | #define INFINEON 0x2 | 5215 | #define INFINEON 0x2 |
@@ -4569,10 +5225,11 @@ typedef struct _ATOM_MC_INIT_PARAM_TABLE | |||
4569 | #define QIMONDA INFINEON | 5225 | #define QIMONDA INFINEON |
4570 | #define PROMOS MOSEL | 5226 | #define PROMOS MOSEL |
4571 | #define KRETON INFINEON | 5227 | #define KRETON INFINEON |
5228 | #define ELIXIR NANYA | ||
4572 | 5229 | ||
4573 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// | 5230 | /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// |
4574 | 5231 | ||
4575 | #define UCODE_ROM_START_ADDRESS 0x1c000 | 5232 | #define UCODE_ROM_START_ADDRESS 0x1b800 |
4576 | #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode | 5233 | #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode |
4577 | 5234 | ||
4578 | //uCode block header for reference | 5235 | //uCode block header for reference |
@@ -4903,7 +5560,34 @@ typedef struct _ATOM_VRAM_MODULE_V6 | |||
4903 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock | 5560 | ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock |
4904 | }ATOM_VRAM_MODULE_V6; | 5561 | }ATOM_VRAM_MODULE_V6; |
4905 | 5562 | ||
4906 | 5563 | typedef struct _ATOM_VRAM_MODULE_V7 | |
5564 | { | ||
5565 | // Design Specific Values | ||
5566 | ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP | ||
5567 | USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 | ||
5568 | USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) | ||
5569 | USHORT usReserved; | ||
5570 | UCHAR ucExtMemoryID; // Current memory module ID | ||
5571 | UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 | ||
5572 | UCHAR ucChannelNum; // Number of mem. channels supported in this module | ||
5573 | UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT | ||
5574 | UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 | ||
5575 | UCHAR ucReserve; // Former container for Mx_FLAGS like DBI_AC_MODE_ENABLE_ASIC for GDDR4. Not used now. | ||
5576 | UCHAR ucMisc; // RANK_OF_THISMEMORY etc. | ||
5577 | UCHAR ucVREFI; // Not used. | ||
5578 | UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. | ||
5579 | UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble | ||
5580 | UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros | ||
5581 | UCHAR ucReserved[3]; | ||
5582 | // Memory Module specific values | ||
5583 | USHORT usEMRS2Value; // EMRS2/MR2 Value. | ||
5584 | USHORT usEMRS3Value; // EMRS3/MR3 Value. | ||
5585 | UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code | ||
5586 | UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) | ||
5587 | UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory | ||
5588 | UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth | ||
5589 | char strMemPNString[20]; // part number end with '0'. | ||
5590 | }ATOM_VRAM_MODULE_V7; | ||
4907 | 5591 | ||
4908 | typedef struct _ATOM_VRAM_INFO_V2 | 5592 | typedef struct _ATOM_VRAM_INFO_V2 |
4909 | { | 5593 | { |
@@ -4942,6 +5626,20 @@ typedef struct _ATOM_VRAM_INFO_V4 | |||
4942 | // ATOM_INIT_REG_BLOCK aMemAdjust; | 5626 | // ATOM_INIT_REG_BLOCK aMemAdjust; |
4943 | }ATOM_VRAM_INFO_V4; | 5627 | }ATOM_VRAM_INFO_V4; |
4944 | 5628 | ||
5629 | typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 | ||
5630 | { | ||
5631 | ATOM_COMMON_TABLE_HEADER sHeader; | ||
5632 | USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting | ||
5633 | USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting | ||
5634 | USHORT usReserved[4]; | ||
5635 | UCHAR ucNumOfVRAMModule; // indicate number of VRAM module | ||
5636 | UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list | ||
5637 | UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version | ||
5638 | UCHAR ucReserved; | ||
5639 | ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; | ||
5640 | }ATOM_VRAM_INFO_HEADER_V2_1; | ||
5641 | |||
5642 | |||
4945 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO | 5643 | typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO |
4946 | { | 5644 | { |
4947 | ATOM_COMMON_TABLE_HEADER sHeader; | 5645 | ATOM_COMMON_TABLE_HEADER sHeader; |
@@ -5182,6 +5880,16 @@ typedef struct _ASIC_TRANSMITTER_INFO | |||
5182 | UCHAR ucReserved; | 5880 | UCHAR ucReserved; |
5183 | }ASIC_TRANSMITTER_INFO; | 5881 | }ASIC_TRANSMITTER_INFO; |
5184 | 5882 | ||
5883 | #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 | ||
5884 | #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 | ||
5885 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 | ||
5886 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 | ||
5887 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 | ||
5888 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 | ||
5889 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 | ||
5890 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 | ||
5891 | #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 | ||
5892 | |||
5185 | typedef struct _ASIC_ENCODER_INFO | 5893 | typedef struct _ASIC_ENCODER_INFO |
5186 | { | 5894 | { |
5187 | UCHAR ucEncoderID; | 5895 | UCHAR ucEncoderID; |
@@ -5284,6 +5992,28 @@ typedef struct _DP_ENCODER_SERVICE_PARAMETERS | |||
5284 | /* /obselete */ | 5992 | /* /obselete */ |
5285 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS | 5993 | #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS |
5286 | 5994 | ||
5995 | |||
5996 | typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 | ||
5997 | { | ||
5998 | USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION | ||
5999 | UCHAR ucAuxId; | ||
6000 | UCHAR ucAction; | ||
6001 | UCHAR ucSinkType; // Iput and Output parameters. | ||
6002 | UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION | ||
6003 | UCHAR ucReserved[2]; | ||
6004 | }DP_ENCODER_SERVICE_PARAMETERS_V2; | ||
6005 | |||
6006 | typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 | ||
6007 | { | ||
6008 | DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; | ||
6009 | PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; | ||
6010 | }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; | ||
6011 | |||
6012 | // ucAction | ||
6013 | #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 | ||
6014 | #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 | ||
6015 | |||
6016 | |||
5287 | // DP_TRAINING_TABLE | 6017 | // DP_TRAINING_TABLE |
5288 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR | 6018 | #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR |
5289 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) | 6019 | #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) |
@@ -5339,6 +6069,7 @@ typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 | |||
5339 | #define SELECT_DCIO_IMPCAL 4 | 6069 | #define SELECT_DCIO_IMPCAL 4 |
5340 | #define SELECT_DCIO_DIG 6 | 6070 | #define SELECT_DCIO_DIG 6 |
5341 | #define SELECT_CRTC_PIXEL_RATE 7 | 6071 | #define SELECT_CRTC_PIXEL_RATE 7 |
6072 | #define SELECT_VGA_BLK 8 | ||
5342 | 6073 | ||
5343 | /****************************************************************************/ | 6074 | /****************************************************************************/ |
5344 | //Portion VI: Definitinos for vbios MC scratch registers that driver used | 6075 | //Portion VI: Definitinos for vbios MC scratch registers that driver used |