aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2014-08-09 14:10:27 -0400
committerBen Skeggs <bskeggs@redhat.com>2014-08-09 15:28:09 -0400
commita3761fa2483f48d158234760d5e25e5071e41537 (patch)
treeba1568228d397d0682296188e586fb12aaffa71d /drivers/gpu/drm/nouveau
parente00f2235386484cc1920dd99d17beac2a8dc4a95 (diff)
drm/nv50-/disp: audit and version LVDS_SCRIPT method
The full object interfaces are about to be exposed to userspace, so we need to check for any security-related issues and version the structs to make it easier to handle any changes we may need in the future. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c16
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv84.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv94.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nva3.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c1
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c4
-rw-r--r--drivers/gpu/drm/nouveau/core/include/core/class.h2
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c33
-rw-r--r--drivers/gpu/drm/nouveau/nvif/class.h7
9 files changed, 43 insertions, 23 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index bb5caa7e2176..93e06ae67c66 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -913,6 +913,21 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
913 if (!priv->sor.hdmi) 913 if (!priv->sor.hdmi)
914 return -ENODEV; 914 return -ENODEV;
915 return priv->sor.hdmi(object, priv, data, size, head, outp); 915 return priv->sor.hdmi(object, priv, data, size, head, outp);
916 case NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT: {
917 union {
918 struct nv50_disp_sor_lvds_script_v0 v0;
919 } *args = data;
920 nv_ioctl(object, "disp sor lvds script size %d\n", size);
921 if (nvif_unpack(args->v0, 0, 0, false)) {
922 nv_ioctl(object, "disp sor lvds script "
923 "vers %d name %04x\n",
924 args->v0.version, args->v0.script);
925 priv->sor.lvdsconf = args->v0.script;
926 return 0;
927 } else
928 return ret;
929 }
930 break;
916 default: 931 default:
917 break; 932 break;
918 } 933 }
@@ -1041,7 +1056,6 @@ nv50_disp_base_ofuncs = {
1041static struct nouveau_omthds 1056static struct nouveau_omthds
1042nv50_disp_base_omthds[] = { 1057nv50_disp_base_omthds[] = {
1043 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, 1058 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
1044 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
1045 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, 1059 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
1046 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, 1060 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
1047 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, 1061 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
index 49cbecf981e6..006ccec6be23 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv84.c
@@ -215,7 +215,6 @@ nv84_disp_sclass[] = {
215struct nouveau_omthds 215struct nouveau_omthds
216nv84_disp_base_omthds[] = { 216nv84_disp_base_omthds[] = {
217 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, 217 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
218 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
219 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, 218 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
220 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, 219 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
221 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd }, 220 { PIOR_MTHD(NV50_DISP_PIOR_DP_PWR) , nv50_pior_mthd },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
index 7234237f4031..f926e967f19d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv94.c
@@ -74,7 +74,6 @@ nv94_disp_sclass[] = {
74static struct nouveau_omthds 74static struct nouveau_omthds
75nv94_disp_base_omthds[] = { 75nv94_disp_base_omthds[] = {
76 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, 76 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
77 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
78 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd }, 77 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
79 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, 78 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
80 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, 79 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
index 488623386cba..e87ee1eee690 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nva3.c
@@ -46,7 +46,6 @@ nva3_disp_sclass[] = {
46static struct nouveau_omthds 46static struct nouveau_omthds
47nva3_disp_base_omthds[] = { 47nva3_disp_base_omthds[] = {
48 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos }, 48 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nv50_disp_base_scanoutpos },
49 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
50 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd }, 49 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
51 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, 50 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
52 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, 51 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
index 7f035f33f25e..bceb7bd2c261 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nvd0.c
@@ -712,7 +712,6 @@ nvd0_disp_base_ofuncs = {
712struct nouveau_omthds 712struct nouveau_omthds
713nvd0_disp_base_omthds[] = { 713nvd0_disp_base_omthds[] = {
714 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nvd0_disp_base_scanoutpos }, 714 { HEAD_MTHD(NV50_DISP_SCANOUTPOS) , nvd0_disp_base_scanoutpos },
715 { SOR_MTHD(NV50_DISP_SOR_LVDS_SCRIPT) , nv50_sor_mthd },
716 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd }, 715 { SOR_MTHD(NV94_DISP_SOR_DP_PWR) , nv50_sor_mthd },
717 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd }, 716 { PIOR_MTHD(NV50_DISP_PIOR_PWR) , nv50_pior_mthd },
718 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd }, 717 { PIOR_MTHD(NV50_DISP_PIOR_TMDS_PWR) , nv50_pior_mthd },
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
index 5f2d71c3f71e..25344feb93cc 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/sornv50.c
@@ -84,10 +84,6 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
84 } 84 }
85 85
86 switch (mthd & ~0x3f) { 86 switch (mthd & ~0x3f) {
87 case NV50_DISP_SOR_LVDS_SCRIPT:
88 priv->sor.lvdsconf = data & NV50_DISP_SOR_LVDS_SCRIPT_ID;
89 ret = 0;
90 break;
91 case NV94_DISP_SOR_DP_PWR: 87 case NV94_DISP_SOR_DP_PWR:
92 if (outp) { 88 if (outp) {
93 struct nvkm_output_dp *outpdp = (void *)outp; 89 struct nvkm_output_dp *outpdp = (void *)outp;
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index e54d9cc54887..d63edc73a7a0 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -59,8 +59,6 @@ struct nv04_display_scanoutpos {
59#define NV50_DISP_SOR_MTHD_LINK 0x00000004 59#define NV50_DISP_SOR_MTHD_LINK 0x00000004
60#define NV50_DISP_SOR_MTHD_OR 0x00000003 60#define NV50_DISP_SOR_MTHD_OR 0x00000003
61 61
62#define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000
63#define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff
64#define NV94_DISP_SOR_DP_PWR 0x00016000 62#define NV94_DISP_SOR_DP_PWR 0x00016000
65#define NV94_DISP_SOR_DP_PWR_STATE 0x00000001 63#define NV94_DISP_SOR_DP_PWR_STATE 0x00000001
66#define NV94_DISP_SOR_DP_PWR_STATE_OFF 0x00000000 64#define NV94_DISP_SOR_DP_PWR_STATE_OFF 0x00000000
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index e83ed52da239..ac80bdc7cbbf 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1882,15 +1882,24 @@ static void
1882nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, 1882nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1883 struct drm_display_mode *mode) 1883 struct drm_display_mode *mode)
1884{ 1884{
1885 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1886 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1887 struct {
1888 struct nv50_disp_mthd_v1 base;
1889 struct nv50_disp_sor_lvds_script_v0 lvds;
1890 } lvds = {
1891 .base.version = 1,
1892 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1893 .base.hasht = nv_encoder->dcb->hasht,
1894 .base.hashm = nv_encoder->dcb->hashm,
1895 };
1885 struct nv50_disp *disp = nv50_disp(encoder->dev); 1896 struct nv50_disp *disp = nv50_disp(encoder->dev);
1886 struct nv50_mast *mast = nv50_mast(encoder->dev); 1897 struct nv50_mast *mast = nv50_mast(encoder->dev);
1887 struct drm_device *dev = encoder->dev; 1898 struct drm_device *dev = encoder->dev;
1888 struct nouveau_drm *drm = nouveau_drm(dev); 1899 struct nouveau_drm *drm = nouveau_drm(dev);
1889 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1890 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1891 struct nouveau_connector *nv_connector; 1900 struct nouveau_connector *nv_connector;
1892 struct nvbios *bios = &drm->vbios; 1901 struct nvbios *bios = &drm->vbios;
1893 u32 lvds = 0, mask, ctrl; 1902 u32 mask, ctrl;
1894 u8 owner = 1 << nv_crtc->index; 1903 u8 owner = 1 << nv_crtc->index;
1895 u8 proto = 0xf; 1904 u8 proto = 0xf;
1896 u8 depth = 0x0; 1905 u8 depth = 0x0;
@@ -1916,31 +1925,31 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1916 1925
1917 if (bios->fp_no_ddc) { 1926 if (bios->fp_no_ddc) {
1918 if (bios->fp.dual_link) 1927 if (bios->fp.dual_link)
1919 lvds |= 0x0100; 1928 lvds.lvds.script |= 0x0100;
1920 if (bios->fp.if_is_24bit) 1929 if (bios->fp.if_is_24bit)
1921 lvds |= 0x0200; 1930 lvds.lvds.script |= 0x0200;
1922 } else { 1931 } else {
1923 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { 1932 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1924 if (((u8 *)nv_connector->edid)[121] == 2) 1933 if (((u8 *)nv_connector->edid)[121] == 2)
1925 lvds |= 0x0100; 1934 lvds.lvds.script |= 0x0100;
1926 } else 1935 } else
1927 if (mode->clock >= bios->fp.duallink_transition_clk) { 1936 if (mode->clock >= bios->fp.duallink_transition_clk) {
1928 lvds |= 0x0100; 1937 lvds.lvds.script |= 0x0100;
1929 } 1938 }
1930 1939
1931 if (lvds & 0x0100) { 1940 if (lvds.lvds.script & 0x0100) {
1932 if (bios->fp.strapless_is_24bit & 2) 1941 if (bios->fp.strapless_is_24bit & 2)
1933 lvds |= 0x0200; 1942 lvds.lvds.script |= 0x0200;
1934 } else { 1943 } else {
1935 if (bios->fp.strapless_is_24bit & 1) 1944 if (bios->fp.strapless_is_24bit & 1)
1936 lvds |= 0x0200; 1945 lvds.lvds.script |= 0x0200;
1937 } 1946 }
1938 1947
1939 if (nv_connector->base.display_info.bpc == 8) 1948 if (nv_connector->base.display_info.bpc == 8)
1940 lvds |= 0x0200; 1949 lvds.lvds.script |= 0x0200;
1941 } 1950 }
1942 1951
1943 nvif_exec(disp->disp, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, &lvds, sizeof(lvds)); 1952 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
1944 break; 1953 break;
1945 case DCB_OUTPUT_DP: 1954 case DCB_OUTPUT_DP:
1946 if (nv_connector->base.display_info.bpc == 6) { 1955 if (nv_connector->base.display_info.bpc == 6) {
diff --git a/drivers/gpu/drm/nouveau/nvif/class.h b/drivers/gpu/drm/nouveau/nvif/class.h
index abc6efab5dc6..a3d433859cbc 100644
--- a/drivers/gpu/drm/nouveau/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/nvif/class.h
@@ -360,4 +360,11 @@ struct nv50_disp_sor_hdmi_pwr_v0 {
360 __u8 pad04[4]; 360 __u8 pad04[4];
361}; 361};
362 362
363struct nv50_disp_sor_lvds_script_v0 {
364 __u8 version;
365 __u8 pad01[1];
366 __u16 script;
367 __u8 pad04[4];
368};
369
363#endif 370#endif