Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

Conflicts:
	Documentation/feature-removal-schedule.txt
	drivers/net/e1000e/netdev.c
	net/xfrm/xfrm_policy.c

14 files changed, 87 insertions, 55 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 2aef5cd3acf5..6bdab891c64e 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -6228,7 +6228,7 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
                 entry->tvconf.has_component_output = false;
                 break;
         case OUTPUT_LVDS:
-                if ((conn & 0x00003f00) != 0x10)
+                if ((conn & 0x00003f00) >> 8 != 0x10)
                         entry->lvdsconf.use_straps_for_mode = true;
                 entry->lvdsconf.use_power_scripts = true;
                 break;
@@ -6310,6 +6310,9 @@ void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
 static bool
 apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
 {
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct dcb_table *dcb = &dev_priv->vbios.dcb;
+
         /* Dell Precision M6300
          *   DCB entry 2: 02025312 00000010
          *   DCB entry 3: 02026312 00000020
@@ -6327,6 +6330,18 @@ apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
                         return false;
         }
 
+        /* GeForce3 Ti 200
+         *
+         * DCB reports an LVDS output that should be TMDS:
+         *   DCB entry 1: f2005014 ffffffff
+         */
+        if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
+                if (*conn == 0xf2005014 && *conf == 0xffffffff) {
+                        fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
+                        return false;
+                }
+        }
+
         return true;
 }
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index a7fae26f4654..d38a4d9f9b0b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -128,6 +128,7 @@ nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
                 }
         }
 
+        nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
         nouveau_bo_placement_set(nvbo, flags, 0);
 
         nvbo->channel = chan;
@@ -166,17 +167,17 @@ static void
 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
 {
         struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
+        int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
 
         if (dev_priv->card_type == NV_10 &&
-            nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM)) {
+            nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
+            nvbo->bo.mem.num_pages < vram_pages / 2) {
                 /*
                  * Make sure that the color and depth buffers are handled
                  * by independent memory controller units. Up to a 9x
                  * speed up when alpha-blending and depth-test are enabled
                  * at the same time.
                  */
-                int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
-
                 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
                         nvbo->placement.fpfn = vram_pages / 2;
                         nvbo->placement.lpfn = ~0;
@@ -785,7 +786,7 @@ nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
         if (ret)
                 goto out;
 
-        ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
+        ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
 out:
         ttm_bo_mem_put(bo, &tmp_mem);
         return ret;
@@ -811,11 +812,11 @@ nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
         if (ret)
                 return ret;
 
-        ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
+        ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
         if (ret)
                 goto out;
 
-        ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
+        ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
         if (ret)
                 goto out;
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index a21e00076839..390d82c3c4b0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -507,6 +507,7 @@ nouveau_connector_native_mode(struct drm_connector *connector)
         int high_w = 0, high_h = 0, high_v = 0;
 
         list_for_each_entry(mode, &nv_connector->base.probed_modes, head) {
+                mode->vrefresh = drm_mode_vrefresh(mode);
                 if (helper->mode_valid(connector, mode) != MODE_OK ||
                     (mode->flags & DRM_MODE_FLAG_INTERLACE))
                         continue;
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 13bb672a16f4..f658a04eecf9 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -234,9 +234,9 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state)
                 pci_set_power_state(pdev, PCI_D3hot);
         }
 
-        acquire_console_sem();
+        console_lock();
         nouveau_fbcon_set_suspend(dev, 1);
-        release_console_sem();
+        console_unlock();
         nouveau_fbcon_restore_accel(dev);
         return 0;
 
@@ -359,9 +359,9 @@ nouveau_pci_resume(struct pci_dev *pdev)
                 nv_crtc->lut.depth = 0;
         }
 
-        acquire_console_sem();
+        console_lock();
         nouveau_fbcon_set_suspend(dev, 0);
-        release_console_sem();
+        console_unlock();
 
         nouveau_fbcon_zfill_all(dev);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 01bffc4412d2..9821fcacc3d2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -848,9 +848,6 @@ extern void nv10_mem_put_tile_region(struct drm_device *dev,
                                      struct nouveau_fence *fence);
 extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
 
-/* nvc0_vram.c */
-extern const struct ttm_mem_type_manager_func nvc0_vram_manager;
-
 /* nouveau_notifier.c */
 extern int  nouveau_notifier_init_channel(struct nouveau_channel *);
 extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index fb846a3fef15..4399e2f34db4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -443,7 +443,7 @@ nouveau_hwmon_fini(struct drm_device *dev)
         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
 
         if (pm->hwmon) {
-                sysfs_remove_group(&pm->hwmon->kobj, &hwmon_attrgroup);
+                sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup);
                 hwmon_device_unregister(pm->hwmon);
         }
 #endif
@@ -543,7 +543,7 @@ nouveau_pm_resume(struct drm_device *dev)
         struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
         struct nouveau_pm_level *perflvl;
 
-        if (pm->cur == &pm->boot)
+        if (!pm->cur || pm->cur == &pm->boot)
                 return;
 
         perflvl = pm->cur;
diff --git a/drivers/gpu/drm/nouveau/nouveau_temp.c b/drivers/gpu/drm/nouveau/nouveau_temp.c
index 7ecc4adc1e45..8d9968e1cba8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_temp.c
+++ b/drivers/gpu/drm/nouveau/nouveau_temp.c
@@ -265,8 +265,8 @@ nouveau_temp_probe_i2c(struct drm_device *dev)
         struct i2c_board_info info[] = {
                 { I2C_BOARD_INFO("w83l785ts", 0x2d) },
                 { I2C_BOARD_INFO("w83781d", 0x2d) },
-                { I2C_BOARD_INFO("f75375", 0x2e) },
                 { I2C_BOARD_INFO("adt7473", 0x2e) },
+                { I2C_BOARD_INFO("f75375", 0x2e) },
                 { I2C_BOARD_INFO("lm99", 0x4c) },
                 { }
         };
diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c
index ef23550407b5..c82db37d9f41 100644
--- a/drivers/gpu/drm/nouveau/nv04_dfp.c
+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c
@@ -342,8 +342,8 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder,
         if (nv_encoder->dcb->type == OUTPUT_LVDS) {
                 bool duallink, dummy;
 
-                nouveau_bios_parse_lvds_table(dev, nv_connector->native_mode->
-                                              clock, &duallink, &dummy);
+                nouveau_bios_parse_lvds_table(dev, output_mode->clock,
+                                              &duallink, &dummy);
                 if (duallink)
                         regp->fp_control |= (8 << 28);
         } else
@@ -518,8 +518,6 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
                 return;
 
         if (nv_encoder->dcb->lvdsconf.use_power_scripts) {
-                struct nouveau_connector *nv_connector = nouveau_encoder_connector_get(nv_encoder);
-
                 /* when removing an output, crtc may not be set, but PANEL_OFF
                  * must still be run
                  */
@@ -527,12 +525,8 @@ static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode)
                            nv04_dfp_get_bound_head(dev, nv_encoder->dcb);
 
                 if (mode == DRM_MODE_DPMS_ON) {
-                        if (!nv_connector->native_mode) {
-                                NV_ERROR(dev, "Not turning on LVDS without native mode\n");
-                                return;
-                        }
                         call_lvds_script(dev, nv_encoder->dcb, head,
-                                         LVDS_PANEL_ON, nv_connector->native_mode->clock);
+                                         LVDS_PANEL_ON, nv_encoder->mode.clock);
                 } else
                         /* pxclk of 0 is fine for PANEL_OFF, and for a
                          * disconnected LVDS encoder there is no native_mode
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 8870d72388c8..18d30c2c1aa6 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -211,18 +211,32 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i)
         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
 
         switch (dev_priv->chipset) {
+        case 0x40:
+        case 0x41: /* guess */
+        case 0x42:
+        case 0x43:
+        case 0x45: /* guess */
+        case 0x4e:
+                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
+                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
+                nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
+                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
+                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
+                nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
+                break;
         case 0x44:
         case 0x4a:
-        case 0x4e:
                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
                 break;
-
         case 0x46:
         case 0x47:
         case 0x49:
         case 0x4b:
+        case 0x4c:
+        case 0x67:
+        default:
                 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
                 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
                 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
@@ -230,15 +244,6 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i)
                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
                 break;
-
-        default:
-                nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
-                nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
-                nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
-                nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
-                nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
-                nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
-                break;
         }
 }
 
@@ -396,17 +401,20 @@ nv40_graph_init(struct drm_device *dev)
                 break;
         default:
                 switch (dev_priv->chipset) {
-                case 0x46:
-                case 0x47:
-                case 0x49:
-                case 0x4b:
-                        nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
-                        nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
-                        break;
-                default:
+                case 0x41:
+                case 0x42:
+                case 0x43:
+                case 0x45:
+                case 0x4e:
+                case 0x44:
+                case 0x4a:
                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
                         break;
+                default:
+                        nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
+                        nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
+                        break;
                 }
                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index 14e24e906ee8..0ea090f4244a 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -283,8 +283,7 @@ nv50_evo_create(struct drm_device *dev)
                         nv50_evo_channel_del(&dev_priv->evo);
                         return ret;
                 }
-        } else
-        if (dev_priv->chipset != 0x50) {
+        } else {
                 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
                                           0, 0xffffffff, 0x00010000);
                 if (ret) {
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 2d7ea75a09d4..37e21d2be95b 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -256,6 +256,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
         int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
         unsigned long flags;
 
@@ -265,6 +266,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
                 return;
 
         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+        pfifo->reassign(dev, false);
         pgraph->fifo_access(dev, false);
 
         if (pgraph->channel(dev) == chan)
@@ -275,6 +277,7 @@ nv50_graph_destroy_context(struct nouveau_channel *chan)
         dev_priv->engine.instmem.flush(dev);
 
         pgraph->fifo_access(dev, true);
+        pfifo->reassign(dev, true);
         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c
index 38e523e10995..459ff08241e5 100644
--- a/drivers/gpu/drm/nouveau/nv50_vm.c
+++ b/drivers/gpu/drm/nouveau/nv50_vm.c
@@ -45,11 +45,6 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
         }
 
         if (phys & 1) {
-                if (dev_priv->vram_sys_base) {
-                        phys += dev_priv->vram_sys_base;
-                        phys |= 0x30;
-                }
-
                 if (coverage <= 32 * 1024 * 1024)
                         phys |= 0x60;
                 else if (coverage <= 64 * 1024 * 1024)
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index e6ea7d83187f..eb18a7e89f5b 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -31,6 +31,7 @@
 #include "nvc0_graph.h"
 
 static void nvc0_graph_isr(struct drm_device *);
+static void nvc0_runk140_isr(struct drm_device *);
 static int  nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
 
 void
@@ -281,6 +282,7 @@ nvc0_graph_destroy(struct drm_device *dev)
                 return;
 
         nouveau_irq_unregister(dev, 12);
+        nouveau_irq_unregister(dev, 25);
 
         nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
         nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
@@ -390,6 +392,7 @@ nvc0_graph_create(struct drm_device *dev)
         }
 
         nouveau_irq_register(dev, 12, nvc0_graph_isr);
+        nouveau_irq_register(dev, 25, nvc0_runk140_isr);
         NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
         NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
         NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
@@ -512,8 +515,8 @@ nvc0_graph_init_gpc_1(struct drm_device *dev)
                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
                         nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
-                        nv_wr32(dev, TP_UNIT(gpc, tp, 0xe44), 0x001ffffe);
-                        nv_wr32(dev, TP_UNIT(gpc, tp, 0xe4c), 0x0000000f);
+                        nv_wr32(dev, TP_UNIT(gpc, tp, 0x644), 0x001ffffe);
+                        nv_wr32(dev, TP_UNIT(gpc, tp, 0x64c), 0x0000000f);
                 }
                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
                 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
@@ -777,3 +780,19 @@ nvc0_graph_isr(struct drm_device *dev)
 
         nv_wr32(dev, 0x400500, 0x00010001);
 }
+
+static void
+nvc0_runk140_isr(struct drm_device *dev)
+{
+        u32 units = nv_rd32(dev, 0x00017c) & 0x1f;
+
+        while (units) {
+                u32 unit = ffs(units) - 1;
+                u32 reg = 0x140000 + unit * 0x2000;
+                u32 st0 = nv_mask(dev, reg + 0x1020, 0, 0);
+                u32 st1 = nv_mask(dev, reg + 0x1420, 0, 0);
+
+                NV_INFO(dev, "PRUNK140: %d 0x%08x 0x%08x\n", unit, st0, st1);
+                units &= ~(1 << unit);
+        }
+}
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index b9e68b2d30aa..f880ff776db8 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1830,7 +1830,7 @@ nvc0_grctx_generate(struct nouveau_channel *chan)
 
         for (tp = 0, id = 0; tp < 4; tp++) {
                 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
-                        if (tp <= priv->tp_nr[gpc]) {
+                        if (tp < priv->tp_nr[gpc]) {
                                 nv_wr32(dev, TP_UNIT(gpc, tp, 0x698), id);
                                 nv_wr32(dev, TP_UNIT(gpc, tp, 0x4e8), id);
                                 nv_wr32(dev, GPC_UNIT(gpc, 0x0c10 + tp * 4), id);