diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2014-09-07 22:48:31 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2014-09-15 08:25:08 -0400 |
commit | d9b5f261db53db32d528698fa2330f6cda1a6292 (patch) | |
tree | be838ea091fd2c831820bd58750eb2b06b32bef2 /drivers/gpu/drm/nouveau | |
parent | 595d373f1e9c9ce0fc946457fdb488e8a58972cd (diff) |
drm/nouveau/bios: parse freq ranges and timing id into ramcfg struct
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
7 files changed, 47 insertions, 26 deletions
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h index c086ac6d677d..bae3ba2dfa1d 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/ramcfg.h | |||
@@ -4,11 +4,18 @@ | |||
4 | struct nouveau_bios; | 4 | struct nouveau_bios; |
5 | 5 | ||
6 | struct nvbios_ramcfg { | 6 | struct nvbios_ramcfg { |
7 | unsigned rammap_ver; | ||
8 | unsigned rammap_hdr; | ||
9 | unsigned rammap_min; | ||
10 | unsigned rammap_max; | ||
7 | unsigned rammap_11_08_01:1; | 11 | unsigned rammap_11_08_01:1; |
8 | unsigned rammap_11_08_0c:2; | 12 | unsigned rammap_11_08_0c:2; |
9 | unsigned rammap_11_08_10:1; | 13 | unsigned rammap_11_08_10:1; |
10 | unsigned rammap_11_11_0c:2; | 14 | unsigned rammap_11_11_0c:2; |
11 | 15 | ||
16 | unsigned ramcfg_ver; | ||
17 | unsigned ramcfg_hdr; | ||
18 | unsigned ramcfg_timing; | ||
12 | unsigned ramcfg_11_01_01:1; | 19 | unsigned ramcfg_11_01_01:1; |
13 | unsigned ramcfg_11_01_02:1; | 20 | unsigned ramcfg_11_01_02:1; |
14 | unsigned ramcfg_11_01_04:1; | 21 | unsigned ramcfg_11_01_04:1; |
@@ -43,6 +50,8 @@ struct nvbios_ramcfg { | |||
43 | unsigned ramcfg_11_08_20:1; | 50 | unsigned ramcfg_11_08_20:1; |
44 | unsigned ramcfg_11_09:8; | 51 | unsigned ramcfg_11_09:8; |
45 | 52 | ||
53 | unsigned timing_ver; | ||
54 | unsigned timing_hdr; | ||
46 | unsigned timing[11]; | 55 | unsigned timing[11]; |
47 | unsigned timing_20_2e_03:2; | 56 | unsigned timing_20_2e_03:2; |
48 | unsigned timing_20_2e_30:2; | 57 | unsigned timing_20_2e_30:2; |
diff --git a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h index 5bdf8e4db40a..47e021d3e20d 100644 --- a/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h +++ b/drivers/gpu/drm/nouveau/core/include/subdev/bios/rammap.h | |||
@@ -8,9 +8,10 @@ u32 nvbios_rammapTe(struct nouveau_bios *, u8 *ver, u8 *hdr, | |||
8 | 8 | ||
9 | u32 nvbios_rammapEe(struct nouveau_bios *, int idx, | 9 | u32 nvbios_rammapEe(struct nouveau_bios *, int idx, |
10 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | 10 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); |
11 | u32 nvbios_rammapEp(struct nouveau_bios *, int idx, | ||
12 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
13 | struct nvbios_ramcfg *); | ||
11 | u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz, | 14 | u32 nvbios_rammapEm(struct nouveau_bios *, u16 mhz, |
12 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len); | ||
13 | u32 nvbios_rammapEp(struct nouveau_bios *, u16 mhz, | ||
14 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | 15 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
15 | struct nvbios_ramcfg *); | 16 | struct nvbios_ramcfg *); |
16 | 17 | ||
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c index 1811b2cb0472..775f7735e0bd 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/rammap.c | |||
@@ -75,28 +75,18 @@ nvbios_rammapEe(struct nouveau_bios *bios, int idx, | |||
75 | } | 75 | } |
76 | 76 | ||
77 | u32 | 77 | u32 |
78 | nvbios_rammapEm(struct nouveau_bios *bios, u16 khz, | 78 | nvbios_rammapEp(struct nouveau_bios *bios, int idx, |
79 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len) | ||
80 | { | ||
81 | int idx = 0; | ||
82 | u32 data; | ||
83 | while ((data = nvbios_rammapEe(bios, idx++, ver, hdr, cnt, len))) { | ||
84 | if (khz >= nv_ro16(bios, data + 0x00) && | ||
85 | khz <= nv_ro16(bios, data + 0x02)) | ||
86 | break; | ||
87 | } | ||
88 | return data; | ||
89 | } | ||
90 | |||
91 | u32 | ||
92 | nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, | ||
93 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | 79 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, |
94 | struct nvbios_ramcfg *p) | 80 | struct nvbios_ramcfg *p) |
95 | { | 81 | { |
96 | u32 data = nvbios_rammapEm(bios, khz, ver, hdr, cnt, len); | 82 | u32 data = nvbios_rammapEe(bios, idx, ver, hdr, cnt, len); |
97 | memset(p, 0x00, sizeof(*p)); | 83 | memset(p, 0x00, sizeof(*p)); |
84 | p->rammap_ver = *ver; | ||
85 | p->rammap_hdr = *hdr; | ||
98 | switch (!!data * *ver) { | 86 | switch (!!data * *ver) { |
99 | case 0x11: | 87 | case 0x11: |
88 | p->rammap_min = nv_ro16(bios, data + 0x00); | ||
89 | p->rammap_max = nv_ro16(bios, data + 0x02); | ||
100 | p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; | 90 | p->rammap_11_08_01 = (nv_ro08(bios, data + 0x08) & 0x01) >> 0; |
101 | p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; | 91 | p->rammap_11_08_0c = (nv_ro08(bios, data + 0x08) & 0x0c) >> 2; |
102 | p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; | 92 | p->rammap_11_08_10 = (nv_ro08(bios, data + 0x08) & 0x10) >> 4; |
@@ -110,6 +100,20 @@ nvbios_rammapEp(struct nouveau_bios *bios, u16 khz, | |||
110 | } | 100 | } |
111 | 101 | ||
112 | u32 | 102 | u32 |
103 | nvbios_rammapEm(struct nouveau_bios *bios, u16 mhz, | ||
104 | u8 *ver, u8 *hdr, u8 *cnt, u8 *len, | ||
105 | struct nvbios_ramcfg *info) | ||
106 | { | ||
107 | int idx = 0; | ||
108 | u32 data; | ||
109 | while ((data = nvbios_rammapEp(bios, idx++, ver, hdr, cnt, len, info))) { | ||
110 | if (mhz >= info->rammap_min && mhz <= info->rammap_max) | ||
111 | break; | ||
112 | } | ||
113 | return data; | ||
114 | } | ||
115 | |||
116 | u32 | ||
113 | nvbios_rammapSe(struct nouveau_bios *bios, u32 data, | 117 | nvbios_rammapSe(struct nouveau_bios *bios, u32 data, |
114 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, | 118 | u8 ever, u8 ehdr, u8 ecnt, u8 elen, int idx, |
115 | u8 *ver, u8 *hdr) | 119 | u8 *ver, u8 *hdr) |
@@ -129,8 +133,11 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data, | |||
129 | u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) | 133 | u8 *ver, u8 *hdr, struct nvbios_ramcfg *p) |
130 | { | 134 | { |
131 | data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); | 135 | data = nvbios_rammapSe(bios, data, ever, ehdr, ecnt, elen, idx, ver, hdr); |
136 | p->ramcfg_ver = *ver; | ||
137 | p->ramcfg_hdr = *hdr; | ||
132 | switch (!!data * *ver) { | 138 | switch (!!data * *ver) { |
133 | case 0x11: | 139 | case 0x11: |
140 | p->ramcfg_timing = nv_ro08(bios, data + 0x00); | ||
134 | p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; | 141 | p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0; |
135 | p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; | 142 | p->ramcfg_11_01_02 = (nv_ro08(bios, data + 0x01) & 0x02) >> 1; |
136 | p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; | 143 | p->ramcfg_11_01_04 = (nv_ro08(bios, data + 0x01) & 0x04) >> 2; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c index 350d44ab2ba2..c320bfdd1102 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c +++ b/drivers/gpu/drm/nouveau/core/subdev/bios/timing.c | |||
@@ -89,6 +89,8 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx, | |||
89 | struct nvbios_ramcfg *p) | 89 | struct nvbios_ramcfg *p) |
90 | { | 90 | { |
91 | u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; | 91 | u16 data = nvbios_timingEe(bios, idx, ver, hdr, cnt, len), temp; |
92 | p->timing_ver = *ver; | ||
93 | p->timing_hdr = *hdr; | ||
92 | switch (!!data * *ver) { | 94 | switch (!!data * *ver) { |
93 | case 0x20: | 95 | case 0x20: |
94 | p->timing[0] = nv_ro32(bios, data + 0x00); | 96 | p->timing[0] = nv_ro32(bios, data + 0x00); |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c index 686e0d679d17..b3c53d6dd82a 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnva3.c | |||
@@ -79,6 +79,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
79 | struct nva3_ram *ram = (void *)pfb->ram; | 79 | struct nva3_ram *ram = (void *)pfb->ram; |
80 | struct nva3_ramfuc *fuc = &ram->fuc; | 80 | struct nva3_ramfuc *fuc = &ram->fuc; |
81 | struct nva3_clock_info mclk; | 81 | struct nva3_clock_info mclk; |
82 | struct nvbios_ramcfg cfg; | ||
82 | u8 ver, cnt, len, strap; | 83 | u8 ver, cnt, len, strap; |
83 | u32 data; | 84 | u32 data; |
84 | struct { | 85 | struct { |
@@ -91,7 +92,7 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
91 | 92 | ||
92 | /* lookup memory config data relevant to the target frequency */ | 93 | /* lookup memory config data relevant to the target frequency */ |
93 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, | 94 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, |
94 | &cnt, &ramcfg.size); | 95 | &cnt, &ramcfg.size, &cfg); |
95 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { | 96 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { |
96 | nv_error(pfb, "invalid/missing rammap entry\n"); | 97 | nv_error(pfb, "invalid/missing rammap entry\n"); |
97 | return -EINVAL; | 98 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c index fc9de888fa81..735cb9580abe 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnvc0.c | |||
@@ -133,6 +133,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
133 | struct nouveau_bios *bios = nouveau_bios(pfb); | 133 | struct nouveau_bios *bios = nouveau_bios(pfb); |
134 | struct nvc0_ram *ram = (void *)pfb->ram; | 134 | struct nvc0_ram *ram = (void *)pfb->ram; |
135 | struct nvc0_ramfuc *fuc = &ram->fuc; | 135 | struct nvc0_ramfuc *fuc = &ram->fuc; |
136 | struct nvbios_ramcfg cfg; | ||
136 | u8 ver, cnt, len, strap; | 137 | u8 ver, cnt, len, strap; |
137 | struct { | 138 | struct { |
138 | u32 data; | 139 | u32 data; |
@@ -145,7 +146,7 @@ nvc0_ram_calc(struct nouveau_fb *pfb, u32 freq) | |||
145 | 146 | ||
146 | /* lookup memory config data relevant to the target frequency */ | 147 | /* lookup memory config data relevant to the target frequency */ |
147 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, | 148 | rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size, |
148 | &cnt, &ramcfg.size); | 149 | &cnt, &ramcfg.size, &cfg); |
149 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { | 150 | if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) { |
150 | nv_error(pfb, "invalid/missing rammap entry\n"); | 151 | nv_error(pfb, "invalid/missing rammap entry\n"); |
151 | return -EINVAL; | 152 | return -EINVAL; |
diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c index 51aa29e8f7eb..1fa45c5e50d7 100644 --- a/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c +++ b/drivers/gpu/drm/nouveau/core/subdev/fb/ramnve0.c | |||
@@ -942,7 +942,7 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, | |||
942 | u8 strap, cnt, len; | 942 | u8 strap, cnt, len; |
943 | 943 | ||
944 | /* lookup memory config data relevant to the target frequency */ | 944 | /* lookup memory config data relevant to the target frequency */ |
945 | ram->base.rammap.data = nvbios_rammapEp(bios, freq / 1000, | 945 | ram->base.rammap.data = nvbios_rammapEm(bios, freq / 1000, |
946 | &ram->base.rammap.version, | 946 | &ram->base.rammap.version, |
947 | &ram->base.rammap.size, | 947 | &ram->base.rammap.size, |
948 | &cnt, &len, &data->bios); | 948 | &cnt, &len, &data->bios); |
@@ -968,12 +968,12 @@ nve0_ram_calc_data(struct nouveau_fb *pfb, u32 freq, | |||
968 | } | 968 | } |
969 | 969 | ||
970 | /* lookup memory timings, if bios says they're present */ | 970 | /* lookup memory timings, if bios says they're present */ |
971 | strap = nv_ro08(bios, ram->base.ramcfg.data + 0x00); | 971 | if (data->bios.ramcfg_timing != 0xff) { |
972 | if (strap != 0xff) { | ||
973 | ram->base.timing.data = | 972 | ram->base.timing.data = |
974 | nvbios_timingEp(bios, strap, &ram->base.timing.version, | 973 | nvbios_timingEp(bios, data->bios.ramcfg_timing, |
975 | &ram->base.timing.size, &cnt, &len, | 974 | &ram->base.timing.version, |
976 | &data->bios); | 975 | &ram->base.timing.size, &cnt, &len, |
976 | &data->bios); | ||
977 | if (!ram->base.timing.data || | 977 | if (!ram->base.timing.data || |
978 | ram->base.timing.version != 0x20 || | 978 | ram->base.timing.version != 0x20 || |
979 | ram->base.timing.size < 0x33) { | 979 | ram->base.timing.size < 0x33) { |