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authorBen Skeggs <bskeggs@redhat.com>2010-07-07 21:53:19 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-07-12 20:13:43 -0400
commitec91db269e6a3c7f45b96169ccf5dbd1fde8fce8 (patch)
tree83c1dd7a6d24533c04578884d0f66d17ad948976 /drivers/gpu/drm/nouveau
parent631872155f35b907ae3950016d9e72a308449d69 (diff)
drm/nouveau: remove ability to use external firmware
This was always really a developer option, and if it's really necessary we can hack this in ourselves. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/Makefile2
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.c4
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h9
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_grctx.c160
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c54
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c64
6 files changed, 49 insertions, 244 deletions
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index acd31ed861ef..4a1db73b3669 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -9,7 +9,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ 9 nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ 10 nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ 11 nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
12 nouveau_dp.o nouveau_grctx.o \ 12 nouveau_dp.o \
13 nv04_timer.o \ 13 nv04_timer.o \
14 nv04_mc.o nv40_mc.o nv50_mc.o \ 14 nv04_mc.o nv40_mc.o nv50_mc.o \
15 nv04_fb.o nv10_fb.o nv40_fb.o nv50_fb.o \ 15 nv04_fb.o nv10_fb.o nv40_fb.o nv50_fb.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 2171dc82c3de..6c8cd38fd116 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -35,10 +35,6 @@
35 35
36#include "drm_pciids.h" 36#include "drm_pciids.h"
37 37
38MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
39int nouveau_ctxfw = 0;
40module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
41
42MODULE_PARM_DESC(noagp, "Disable AGP"); 38MODULE_PARM_DESC(noagp, "Disable AGP");
43int nouveau_noagp; 39int nouveau_noagp;
44module_param_named(noagp, nouveau_noagp, int, 0400); 40module_param_named(noagp, nouveau_noagp, int, 0400);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 6a6873d4b28a..64a080e5a13d 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -330,8 +330,6 @@ struct nouveau_pgraph_object_class {
330struct nouveau_pgraph_engine { 330struct nouveau_pgraph_engine {
331 struct nouveau_pgraph_object_class *grclass; 331 struct nouveau_pgraph_object_class *grclass;
332 bool accel_blocked; 332 bool accel_blocked;
333 void *ctxprog;
334 void *ctxvals;
335 int grctx_size; 333 int grctx_size;
336 334
337 int (*init)(struct drm_device *); 335 int (*init)(struct drm_device *);
@@ -665,7 +663,6 @@ extern int nouveau_tv_disable;
665extern char *nouveau_tv_norm; 663extern char *nouveau_tv_norm;
666extern int nouveau_reg_debug; 664extern int nouveau_reg_debug;
667extern char *nouveau_vbios; 665extern char *nouveau_vbios;
668extern int nouveau_ctxfw;
669extern int nouveau_ignorelid; 666extern int nouveau_ignorelid;
670extern int nouveau_nofbaccel; 667extern int nouveau_nofbaccel;
671extern int nouveau_noaccel; 668extern int nouveau_noaccel;
@@ -1010,12 +1007,6 @@ extern int nv50_graph_unload_context(struct drm_device *);
1010extern void nv50_graph_context_switch(struct drm_device *); 1007extern void nv50_graph_context_switch(struct drm_device *);
1011extern int nv50_grctx_init(struct nouveau_grctx *); 1008extern int nv50_grctx_init(struct nouveau_grctx *);
1012 1009
1013/* nouveau_grctx.c */
1014extern int nouveau_grctx_prog_load(struct drm_device *);
1015extern void nouveau_grctx_vals_load(struct drm_device *,
1016 struct nouveau_gpuobj *);
1017extern void nouveau_grctx_fini(struct drm_device *);
1018
1019/* nv04_instmem.c */ 1010/* nv04_instmem.c */
1020extern int nv04_instmem_init(struct drm_device *); 1011extern int nv04_instmem_init(struct drm_device *);
1021extern void nv04_instmem_takedown(struct drm_device *); 1012extern void nv04_instmem_takedown(struct drm_device *);
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.c b/drivers/gpu/drm/nouveau/nouveau_grctx.c
deleted file mode 100644
index f731c5f60536..000000000000
--- a/drivers/gpu/drm/nouveau/nouveau_grctx.c
+++ /dev/null
@@ -1,160 +0,0 @@
1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <linux/firmware.h>
26#include <linux/slab.h>
27
28#include "drmP.h"
29#include "nouveau_drv.h"
30
31struct nouveau_ctxprog {
32 uint32_t signature;
33 uint8_t version;
34 uint16_t length;
35 uint32_t data[];
36} __attribute__ ((packed));
37
38struct nouveau_ctxvals {
39 uint32_t signature;
40 uint8_t version;
41 uint32_t length;
42 struct {
43 uint32_t offset;
44 uint32_t value;
45 } data[];
46} __attribute__ ((packed));
47
48int
49nouveau_grctx_prog_load(struct drm_device *dev)
50{
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
53 const int chipset = dev_priv->chipset;
54 const struct firmware *fw;
55 const struct nouveau_ctxprog *cp;
56 const struct nouveau_ctxvals *cv;
57 char name[32];
58 int ret, i;
59
60 if (pgraph->accel_blocked)
61 return -ENODEV;
62
63 if (!pgraph->ctxprog) {
64 sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
65 ret = request_firmware(&fw, name, &dev->pdev->dev);
66 if (ret) {
67 NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
68 return ret;
69 }
70
71 pgraph->ctxprog = kmemdup(fw->data, fw->size, GFP_KERNEL);
72 if (!pgraph->ctxprog) {
73 NV_ERROR(dev, "OOM copying ctxprog\n");
74 release_firmware(fw);
75 return -ENOMEM;
76 }
77
78 cp = pgraph->ctxprog;
79 if (le32_to_cpu(cp->signature) != 0x5043564e ||
80 cp->version != 0 ||
81 le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
82 NV_ERROR(dev, "ctxprog invalid\n");
83 release_firmware(fw);
84 nouveau_grctx_fini(dev);
85 return -EINVAL;
86 }
87 release_firmware(fw);
88 }
89
90 if (!pgraph->ctxvals) {
91 sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
92 ret = request_firmware(&fw, name, &dev->pdev->dev);
93 if (ret) {
94 NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
95 nouveau_grctx_fini(dev);
96 return ret;
97 }
98
99 pgraph->ctxvals = kmemdup(fw->data, fw->size, GFP_KERNEL);
100 if (!pgraph->ctxvals) {
101 NV_ERROR(dev, "OOM copying ctxvals\n");
102 release_firmware(fw);
103 nouveau_grctx_fini(dev);
104 return -ENOMEM;
105 }
106
107 cv = (void *)pgraph->ctxvals;
108 if (le32_to_cpu(cv->signature) != 0x5643564e ||
109 cv->version != 0 ||
110 le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
111 NV_ERROR(dev, "ctxvals invalid\n");
112 release_firmware(fw);
113 nouveau_grctx_fini(dev);
114 return -EINVAL;
115 }
116 release_firmware(fw);
117 }
118
119 cp = pgraph->ctxprog;
120
121 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
122 for (i = 0; i < le16_to_cpu(cp->length); i++)
123 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
124 le32_to_cpu(cp->data[i]));
125
126 return 0;
127}
128
129void
130nouveau_grctx_fini(struct drm_device *dev)
131{
132 struct drm_nouveau_private *dev_priv = dev->dev_private;
133 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
134
135 if (pgraph->ctxprog) {
136 kfree(pgraph->ctxprog);
137 pgraph->ctxprog = NULL;
138 }
139
140 if (pgraph->ctxvals) {
141 kfree(pgraph->ctxprog);
142 pgraph->ctxvals = NULL;
143 }
144}
145
146void
147nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
148{
149 struct drm_nouveau_private *dev_priv = dev->dev_private;
150 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
151 struct nouveau_ctxvals *cv = pgraph->ctxvals;
152 int i;
153
154 if (!cv)
155 return;
156
157 for (i = 0; i < le32_to_cpu(cv->length); i++)
158 nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
159 le32_to_cpu(cv->data[i].value));
160}
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 2608c34eca82..fd7d2b501316 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -58,6 +58,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
58 struct drm_device *dev = chan->dev; 58 struct drm_device *dev = chan->dev;
59 struct drm_nouveau_private *dev_priv = dev->dev_private; 59 struct drm_nouveau_private *dev_priv = dev->dev_private;
60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 60 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
61 struct nouveau_grctx ctx = {};
61 int ret; 62 int ret;
62 63
63 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, 64 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
@@ -67,16 +68,11 @@ nv40_graph_create_context(struct nouveau_channel *chan)
67 return ret; 68 return ret;
68 69
69 /* Initialise default context values */ 70 /* Initialise default context values */
70 if (!pgraph->ctxprog) { 71 ctx.dev = chan->dev;
71 struct nouveau_grctx ctx = {}; 72 ctx.mode = NOUVEAU_GRCTX_VALS;
73 ctx.data = chan->ramin_grctx->gpuobj;
74 nv40_grctx_init(&ctx);
72 75
73 ctx.dev = chan->dev;
74 ctx.mode = NOUVEAU_GRCTX_VALS;
75 ctx.data = chan->ramin_grctx->gpuobj;
76 nv40_grctx_init(&ctx);
77 } else {
78 nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
79 }
80 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0, 76 nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
81 chan->ramin_grctx->gpuobj->im_pramin->start); 77 chan->ramin_grctx->gpuobj->im_pramin->start);
82 return 0; 78 return 0;
@@ -236,7 +232,8 @@ nv40_graph_init(struct drm_device *dev)
236 struct drm_nouveau_private *dev_priv = 232 struct drm_nouveau_private *dev_priv =
237 (struct drm_nouveau_private *)dev->dev_private; 233 (struct drm_nouveau_private *)dev->dev_private;
238 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; 234 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
239 uint32_t vramsz; 235 struct nouveau_grctx ctx = {};
236 uint32_t vramsz, *cp;
240 int i, j; 237 int i, j;
241 238
242 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & 239 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -244,32 +241,22 @@ nv40_graph_init(struct drm_device *dev)
244 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | 241 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
245 NV_PMC_ENABLE_PGRAPH); 242 NV_PMC_ENABLE_PGRAPH);
246 243
247 if (nouveau_ctxfw) { 244 cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
248 nouveau_grctx_prog_load(dev); 245 if (!cp)
249 dev_priv->engine.graph.grctx_size = 175 * 1024; 246 return -ENOMEM;
250 }
251
252 if (!dev_priv->engine.graph.ctxprog) {
253 struct nouveau_grctx ctx = {};
254 uint32_t *cp;
255
256 cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
257 if (!cp)
258 return -ENOMEM;
259 247
260 ctx.dev = dev; 248 ctx.dev = dev;
261 ctx.mode = NOUVEAU_GRCTX_PROG; 249 ctx.mode = NOUVEAU_GRCTX_PROG;
262 ctx.data = cp; 250 ctx.data = cp;
263 ctx.ctxprog_max = 256; 251 ctx.ctxprog_max = 256;
264 nv40_grctx_init(&ctx); 252 nv40_grctx_init(&ctx);
265 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; 253 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
266 254
267 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); 255 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
268 for (i = 0; i < ctx.ctxprog_len; i++) 256 for (i = 0; i < ctx.ctxprog_len; i++)
269 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); 257 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
270 258
271 kfree(cp); 259 kfree(cp);
272 }
273 260
274 /* No context present currently */ 261 /* No context present currently */
275 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 262 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -405,7 +392,6 @@ nv40_graph_init(struct drm_device *dev)
405 392
406void nv40_graph_takedown(struct drm_device *dev) 393void nv40_graph_takedown(struct drm_device *dev)
407{ 394{
408 nouveau_grctx_fini(dev);
409} 395}
410 396
411struct nouveau_pgraph_object_class nv40_graph_grclass[] = { 397struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 5dc3be5696a9..395857a34a03 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -103,37 +103,33 @@ static int
103nv50_graph_init_ctxctl(struct drm_device *dev) 103nv50_graph_init_ctxctl(struct drm_device *dev)
104{ 104{
105 struct drm_nouveau_private *dev_priv = dev->dev_private; 105 struct drm_nouveau_private *dev_priv = dev->dev_private;
106 struct nouveau_grctx ctx = {};
107 uint32_t *cp;
108 int i;
106 109
107 NV_DEBUG(dev, "\n"); 110 NV_DEBUG(dev, "\n");
108 111
109 if (nouveau_ctxfw) { 112 cp = kmalloc(512 * 4, GFP_KERNEL);
110 nouveau_grctx_prog_load(dev); 113 if (!cp) {
111 dev_priv->engine.graph.grctx_size = 0x70000; 114 NV_ERROR(dev, "failed to allocate ctxprog\n");
115 dev_priv->engine.graph.accel_blocked = true;
116 return 0;
112 } 117 }
113 if (!dev_priv->engine.graph.ctxprog) { 118
114 struct nouveau_grctx ctx = {}; 119 ctx.dev = dev;
115 uint32_t *cp = kmalloc(512 * 4, GFP_KERNEL); 120 ctx.mode = NOUVEAU_GRCTX_PROG;
116 int i; 121 ctx.data = cp;
117 if (!cp) { 122 ctx.ctxprog_max = 512;
118 NV_ERROR(dev, "Couldn't alloc ctxprog! Disabling acceleration.\n"); 123 if (!nv50_grctx_init(&ctx)) {
119 dev_priv->engine.graph.accel_blocked = true; 124 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
120 return 0; 125
121 } 126 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
122 ctx.dev = dev; 127 for (i = 0; i < ctx.ctxprog_len; i++)
123 ctx.mode = NOUVEAU_GRCTX_PROG; 128 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
124 ctx.data = cp; 129 } else {
125 ctx.ctxprog_max = 512; 130 dev_priv->engine.graph.accel_blocked = true;
126 if (!nv50_grctx_init(&ctx)) {
127 dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
128
129 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
130 for (i = 0; i < ctx.ctxprog_len; i++)
131 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
132 } else {
133 dev_priv->engine.graph.accel_blocked = true;
134 }
135 kfree(cp);
136 } 131 }
132 kfree(cp);
137 133
138 nv_wr32(dev, 0x400320, 4); 134 nv_wr32(dev, 0x400320, 4);
139 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0); 135 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
@@ -164,7 +160,6 @@ void
164nv50_graph_takedown(struct drm_device *dev) 160nv50_graph_takedown(struct drm_device *dev)
165{ 161{
166 NV_DEBUG(dev, "\n"); 162 NV_DEBUG(dev, "\n");
167 nouveau_grctx_fini(dev);
168} 163}
169 164
170void 165void
@@ -214,6 +209,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
214 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; 209 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
215 struct nouveau_gpuobj *obj; 210 struct nouveau_gpuobj *obj;
216 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 211 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
212 struct nouveau_grctx ctx = {};
217 int hdr, ret; 213 int hdr, ret;
218 214
219 NV_DEBUG(dev, "ch%d\n", chan->id); 215 NV_DEBUG(dev, "ch%d\n", chan->id);
@@ -234,15 +230,11 @@ nv50_graph_create_context(struct nouveau_channel *chan)
234 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0); 230 nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
235 nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000); 231 nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);
236 232
237 if (!pgraph->ctxprog) { 233 ctx.dev = chan->dev;
238 struct nouveau_grctx ctx = {}; 234 ctx.mode = NOUVEAU_GRCTX_VALS;
239 ctx.dev = chan->dev; 235 ctx.data = obj;
240 ctx.mode = NOUVEAU_GRCTX_VALS; 236 nv50_grctx_init(&ctx);
241 ctx.data = obj; 237
242 nv50_grctx_init(&ctx);
243 } else {
244 nouveau_grctx_vals_load(dev, obj);
245 }
246 nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12); 238 nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
247 239
248 dev_priv->engine.instmem.flush(dev); 240 dev_priv->engine.instmem.flush(dev);