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authorBen Skeggs <bskeggs@redhat.com>2010-11-02 23:16:18 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-12-03 00:11:41 -0500
commit274fec93cdd627408a799519fa602f2eecb14d2f (patch)
tree1ffc788a096237583608dfa3f09caccfc500ec82 /drivers/gpu/drm/nouveau
parent5178d40dff23b5eef7f0a3be2411fa6a347e750d (diff)
drm/nouveau: tidy+move PGRAPH ISRs to their respective *_graph.c files
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_drv.h8
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c894
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_object.c18
-rw-r--r--drivers/gpu/drm/nouveau/nv04_graph.c95
-rw-r--r--drivers/gpu/drm/nouveau/nv10_graph.c72
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c47
-rw-r--r--drivers/gpu/drm/nouveau/nv40_graph.c69
-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c500
8 files changed, 809 insertions, 894 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index e174479ab675..b19ef7fbb9dd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -54,6 +54,7 @@ struct nouveau_fpriv {
54#include "nouveau_drm.h" 54#include "nouveau_drm.h"
55#include "nouveau_reg.h" 55#include "nouveau_reg.h"
56#include "nouveau_bios.h" 56#include "nouveau_bios.h"
57#include "nouveau_util.h"
57struct nouveau_grctx; 58struct nouveau_grctx;
58 59
59#define MAX_NUM_DCB_ENTRIES 16 60#define MAX_NUM_DCB_ENTRIES 16
@@ -872,6 +873,7 @@ extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
872 int (*exec)(struct nouveau_channel *, 873 int (*exec)(struct nouveau_channel *,
873 u32 class, u32 mthd, u32 data)); 874 u32 class, u32 mthd, u32 data));
874extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); 875extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
876extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
875extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, 877extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
876 uint32_t vram_h, uint32_t tt_h); 878 uint32_t vram_h, uint32_t tt_h);
877extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); 879extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
@@ -1110,9 +1112,9 @@ extern int nv04_graph_create_context(struct nouveau_channel *);
1110extern void nv04_graph_destroy_context(struct nouveau_channel *); 1112extern void nv04_graph_destroy_context(struct nouveau_channel *);
1111extern int nv04_graph_load_context(struct nouveau_channel *); 1113extern int nv04_graph_load_context(struct nouveau_channel *);
1112extern int nv04_graph_unload_context(struct drm_device *); 1114extern int nv04_graph_unload_context(struct drm_device *);
1113extern void nv04_graph_context_switch(struct drm_device *);
1114extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, 1115extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1115 u32 class, u32 mthd, u32 data); 1116 u32 class, u32 mthd, u32 data);
1117extern struct nouveau_bitfield nv04_graph_nsource[];
1116 1118
1117/* nv10_graph.c */ 1119/* nv10_graph.c */
1118extern int nv10_graph_init(struct drm_device *); 1120extern int nv10_graph_init(struct drm_device *);
@@ -1122,8 +1124,9 @@ extern int nv10_graph_create_context(struct nouveau_channel *);
1122extern void nv10_graph_destroy_context(struct nouveau_channel *); 1124extern void nv10_graph_destroy_context(struct nouveau_channel *);
1123extern int nv10_graph_load_context(struct nouveau_channel *); 1125extern int nv10_graph_load_context(struct nouveau_channel *);
1124extern int nv10_graph_unload_context(struct drm_device *); 1126extern int nv10_graph_unload_context(struct drm_device *);
1125extern void nv10_graph_context_switch(struct drm_device *);
1126extern void nv10_graph_set_tile_region(struct drm_device *dev, int i); 1127extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
1128extern struct nouveau_bitfield nv10_graph_intr[];
1129extern struct nouveau_bitfield nv10_graph_nstatus[];
1127 1130
1128/* nv20_graph.c */ 1131/* nv20_graph.c */
1129extern int nv20_graph_create_context(struct nouveau_channel *); 1132extern int nv20_graph_create_context(struct nouveau_channel *);
@@ -1155,7 +1158,6 @@ extern int nv50_graph_create_context(struct nouveau_channel *);
1155extern void nv50_graph_destroy_context(struct nouveau_channel *); 1158extern void nv50_graph_destroy_context(struct nouveau_channel *);
1156extern int nv50_graph_load_context(struct nouveau_channel *); 1159extern int nv50_graph_load_context(struct nouveau_channel *);
1157extern int nv50_graph_unload_context(struct drm_device *); 1160extern int nv50_graph_unload_context(struct drm_device *);
1158extern void nv50_graph_context_switch(struct drm_device *);
1159extern int nv50_grctx_init(struct nouveau_grctx *); 1161extern int nv50_grctx_init(struct nouveau_grctx *);
1160extern void nv50_graph_tlb_flush(struct drm_device *dev); 1162extern void nv50_graph_tlb_flush(struct drm_device *dev);
1161extern void nv86_graph_tlb_flush(struct drm_device *dev); 1163extern void nv86_graph_tlb_flush(struct drm_device *dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index 16f42f774a9e..2ba7265bc967 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -69,910 +69,34 @@ nouveau_irq_uninstall(struct drm_device *dev)
69 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0); 69 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
70} 70}
71 71
72static struct nouveau_bitfield nstatus_names[] =
73{
74 { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
75 { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
76 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
77 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
78 {}
79};
80
81static struct nouveau_bitfield nstatus_names_nv10[] =
82{
83 { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
84 { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
85 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
86 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
87 {}
88};
89
90static struct nouveau_bitfield nsource_names[] =
91{
92 { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
93 { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
94 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
95 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
96 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
97 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
98 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
99 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
100 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
101 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
102 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
103 { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
104 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
105 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
106 { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
107 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
108 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
109 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
110 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
111 {}
112};
113
114static int
115nouveau_graph_chid_from_grctx(struct drm_device *dev)
116{
117 struct drm_nouveau_private *dev_priv = dev->dev_private;
118 struct nouveau_channel *chan;
119 unsigned long flags;
120 uint32_t inst;
121 int i;
122
123 if (dev_priv->card_type < NV_40)
124 return dev_priv->engine.fifo.channels;
125 else
126 if (dev_priv->card_type < NV_50) {
127 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4;
128
129 spin_lock_irqsave(&dev_priv->channels.lock, flags);
130 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
131 chan = dev_priv->channels.ptr[i];
132 if (!chan || !chan->ramin_grctx)
133 continue;
134
135 if (inst == chan->ramin_grctx->pinst)
136 break;
137 }
138 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
139 } else {
140 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12;
141
142 spin_lock_irqsave(&dev_priv->channels.lock, flags);
143 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
144 chan = dev_priv->channels.ptr[i];
145 if (!chan || !chan->ramin)
146 continue;
147
148 if (inst == chan->ramin->vinst)
149 break;
150 }
151 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
152 }
153
154
155 return i;
156}
157
158static int
159nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
160{
161 struct drm_nouveau_private *dev_priv = dev->dev_private;
162 struct nouveau_engine *engine = &dev_priv->engine;
163 int channel;
164
165 if (dev_priv->card_type < NV_10)
166 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
167 else
168 if (dev_priv->card_type < NV_40)
169 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
170 else
171 channel = nouveau_graph_chid_from_grctx(dev);
172
173 if (channel >= engine->fifo.channels ||
174 !dev_priv->channels.ptr[channel]) {
175 NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel);
176 return -EINVAL;
177 }
178
179 *channel_ret = channel;
180 return 0;
181}
182
183struct nouveau_pgraph_trap {
184 int channel;
185 int class;
186 int subc, mthd, size;
187 uint32_t data, data2;
188 uint32_t nsource, nstatus;
189};
190
191static void
192nouveau_graph_trap_info(struct drm_device *dev,
193 struct nouveau_pgraph_trap *trap)
194{
195 struct drm_nouveau_private *dev_priv = dev->dev_private;
196 uint32_t address;
197
198 trap->nsource = trap->nstatus = 0;
199 if (dev_priv->card_type < NV_50) {
200 trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
201 trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
202 }
203
204 if (nouveau_graph_trapped_channel(dev, &trap->channel))
205 trap->channel = -1;
206 address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
207
208 trap->mthd = address & 0x1FFC;
209 trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
210 if (dev_priv->card_type < NV_10) {
211 trap->subc = (address >> 13) & 0x7;
212 } else {
213 trap->subc = (address >> 16) & 0x7;
214 trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH);
215 }
216
217 if (dev_priv->card_type < NV_10)
218 trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF;
219 else if (dev_priv->card_type < NV_40)
220 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF;
221 else if (dev_priv->card_type < NV_50)
222 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF;
223 else
224 trap->class = nv_rd32(dev, 0x400814);
225}
226
227static void
228nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
229 struct nouveau_pgraph_trap *trap)
230{
231 struct drm_nouveau_private *dev_priv = dev->dev_private;
232 uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
233
234 if (dev_priv->card_type < NV_50) {
235 NV_INFO(dev, "%s - nSource:", id);
236 nouveau_bitfield_print(nsource_names, nsource);
237 printk(", nStatus:");
238 if (dev_priv->card_type < NV_10)
239 nouveau_bitfield_print(nstatus_names, nstatus);
240 else
241 nouveau_bitfield_print(nstatus_names_nv10, nstatus);
242 printk("\n");
243 }
244
245 NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
246 "Data 0x%08x:0x%08x\n",
247 id, trap->channel, trap->subc,
248 trap->class, trap->mthd,
249 trap->data2, trap->data);
250}
251
252static int
253nouveau_pgraph_intr_swmthd(struct drm_device *dev,
254 struct nouveau_pgraph_trap *trap)
255{
256 struct drm_nouveau_private *dev_priv = dev->dev_private;
257 struct nouveau_channel *chan;
258 unsigned long flags;
259 int ret = -EINVAL;
260
261 spin_lock_irqsave(&dev_priv->channels.lock, flags);
262 if (trap->channel > 0 &&
263 trap->channel < dev_priv->engine.fifo.channels &&
264 dev_priv->channels.ptr[trap->channel]) {
265 chan = dev_priv->channels.ptr[trap->channel];
266 ret = nouveau_gpuobj_mthd_call(chan, trap->class, trap->mthd, trap->data);
267 }
268 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
269
270 return ret;
271}
272
273static inline void
274nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
275{
276 struct nouveau_pgraph_trap trap;
277 int unhandled = 0;
278
279 nouveau_graph_trap_info(dev, &trap);
280
281 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
282 if (nouveau_pgraph_intr_swmthd(dev, &trap))
283 unhandled = 1;
284 } else {
285 unhandled = 1;
286 }
287
288 if (unhandled)
289 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
290}
291
292
293static inline void
294nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
295{
296 struct nouveau_pgraph_trap trap;
297 int unhandled = 0;
298
299 nouveau_graph_trap_info(dev, &trap);
300 trap.nsource = nsource;
301
302 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
303 if (nouveau_pgraph_intr_swmthd(dev, &trap))
304 unhandled = 1;
305 } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
306 uint32_t v = nv_rd32(dev, 0x402000);
307 nv_wr32(dev, 0x402000, v);
308
309 /* dump the error anyway for now: it's useful for
310 Gallium development */
311 unhandled = 1;
312 } else {
313 unhandled = 1;
314 }
315
316 if (unhandled && nouveau_ratelimit())
317 nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
318}
319
320static inline void
321nouveau_pgraph_intr_context_switch(struct drm_device *dev)
322{
323 struct drm_nouveau_private *dev_priv = dev->dev_private;
324 struct nouveau_engine *engine = &dev_priv->engine;
325 uint32_t chid;
326
327 chid = engine->fifo.channel_id(dev);
328 NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid);
329
330 switch (dev_priv->card_type) {
331 case NV_04:
332 nv04_graph_context_switch(dev);
333 break;
334 case NV_10:
335 nv10_graph_context_switch(dev);
336 break;
337 default:
338 NV_ERROR(dev, "Context switch not implemented\n");
339 break;
340 }
341}
342
343static void
344nouveau_pgraph_irq_handler(struct drm_device *dev)
345{
346 uint32_t status;
347
348 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
349 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
350
351 if (status & NV_PGRAPH_INTR_NOTIFY) {
352 nouveau_pgraph_intr_notify(dev, nsource);
353
354 status &= ~NV_PGRAPH_INTR_NOTIFY;
355 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
356 }
357
358 if (status & NV_PGRAPH_INTR_ERROR) {
359 nouveau_pgraph_intr_error(dev, nsource);
360
361 status &= ~NV_PGRAPH_INTR_ERROR;
362 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
363 }
364
365 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
366 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
367 nv_wr32(dev, NV03_PGRAPH_INTR,
368 NV_PGRAPH_INTR_CONTEXT_SWITCH);
369
370 nouveau_pgraph_intr_context_switch(dev);
371 }
372
373 if (status) {
374 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
375 nv_wr32(dev, NV03_PGRAPH_INTR, status);
376 }
377
378 if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
379 nv_wr32(dev, NV04_PGRAPH_FIFO, 1);
380 }
381
382 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
383}
384
385static struct nouveau_enum nv50_mp_exec_error_names[] =
386{
387 { 3, "STACK_UNDERFLOW" },
388 { 4, "QUADON_ACTIVE" },
389 { 8, "TIMEOUT" },
390 { 0x10, "INVALID_OPCODE" },
391 { 0x40, "BREAKPOINT" },
392 {}
393};
394
395static void
396nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
397{
398 struct drm_nouveau_private *dev_priv = dev->dev_private;
399 uint32_t units = nv_rd32(dev, 0x1540);
400 uint32_t addr, mp10, status, pc, oplow, ophigh;
401 int i;
402 int mps = 0;
403 for (i = 0; i < 4; i++) {
404 if (!(units & 1 << (i+24)))
405 continue;
406 if (dev_priv->chipset < 0xa0)
407 addr = 0x408200 + (tpid << 12) + (i << 7);
408 else
409 addr = 0x408100 + (tpid << 11) + (i << 7);
410 mp10 = nv_rd32(dev, addr + 0x10);
411 status = nv_rd32(dev, addr + 0x14);
412 if (!status)
413 continue;
414 if (display) {
415 nv_rd32(dev, addr + 0x20);
416 pc = nv_rd32(dev, addr + 0x24);
417 oplow = nv_rd32(dev, addr + 0x70);
418 ophigh= nv_rd32(dev, addr + 0x74);
419 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
420 "TP %d MP %d: ", tpid, i);
421 nouveau_enum_print(nv50_mp_exec_error_names, status);
422 printk(" at %06x warp %d, opcode %08x %08x\n",
423 pc&0xffffff, pc >> 24,
424 oplow, ophigh);
425 }
426 nv_wr32(dev, addr + 0x10, mp10);
427 nv_wr32(dev, addr + 0x14, 0);
428 mps++;
429 }
430 if (!mps && display)
431 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
432 "No MPs claiming errors?\n", tpid);
433}
434
435static void
436nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
437 uint32_t ustatus_new, int display, const char *name)
438{
439 struct drm_nouveau_private *dev_priv = dev->dev_private;
440 int tps = 0;
441 uint32_t units = nv_rd32(dev, 0x1540);
442 int i, r;
443 uint32_t ustatus_addr, ustatus;
444 for (i = 0; i < 16; i++) {
445 if (!(units & (1 << i)))
446 continue;
447 if (dev_priv->chipset < 0xa0)
448 ustatus_addr = ustatus_old + (i << 12);
449 else
450 ustatus_addr = ustatus_new + (i << 11);
451 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
452 if (!ustatus)
453 continue;
454 tps++;
455 switch (type) {
456 case 6: /* texture error... unknown for now */
457 nv50_fb_vm_trap(dev, display, name);
458 if (display) {
459 NV_ERROR(dev, "magic set %d:\n", i);
460 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
461 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
462 nv_rd32(dev, r));
463 }
464 break;
465 case 7: /* MP error */
466 if (ustatus & 0x00010000) {
467 nv50_pgraph_mp_trap(dev, i, display);
468 ustatus &= ~0x00010000;
469 }
470 break;
471 case 8: /* TPDMA error */
472 {
473 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
474 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
475 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
476 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
477 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
478 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
479 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
480 nv50_fb_vm_trap(dev, display, name);
481 /* 2d engine destination */
482 if (ustatus & 0x00000010) {
483 if (display) {
484 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
485 i, e14, e10);
486 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
487 i, e0c, e18, e1c, e20, e24);
488 }
489 ustatus &= ~0x00000010;
490 }
491 /* Render target */
492 if (ustatus & 0x00000040) {
493 if (display) {
494 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
495 i, e14, e10);
496 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
497 i, e0c, e18, e1c, e20, e24);
498 }
499 ustatus &= ~0x00000040;
500 }
501 /* CUDA memory: l[], g[] or stack. */
502 if (ustatus & 0x00000080) {
503 if (display) {
504 if (e18 & 0x80000000) {
505 /* g[] read fault? */
506 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
507 i, e14, e10 | ((e18 >> 24) & 0x1f));
508 e18 &= ~0x1f000000;
509 } else if (e18 & 0xc) {
510 /* g[] write fault? */
511 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
512 i, e14, e10 | ((e18 >> 7) & 0x1f));
513 e18 &= ~0x00000f80;
514 } else {
515 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
516 i, e14, e10);
517 }
518 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
519 i, e0c, e18, e1c, e20, e24);
520 }
521 ustatus &= ~0x00000080;
522 }
523 }
524 break;
525 }
526 if (ustatus) {
527 if (display)
528 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
529 }
530 nv_wr32(dev, ustatus_addr, 0xc0000000);
531 }
532
533 if (!tps && display)
534 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
535}
536
537static void
538nv50_pgraph_trap_handler(struct drm_device *dev)
539{
540 struct nouveau_pgraph_trap trap;
541 uint32_t status = nv_rd32(dev, 0x400108);
542 uint32_t ustatus;
543 int display = nouveau_ratelimit();
544
545
546 if (!status && display) {
547 nouveau_graph_trap_info(dev, &trap);
548 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
549 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
550 }
551
552 /* DISPATCH: Relays commands to other units and handles NOTIFY,
553 * COND, QUERY. If you get a trap from it, the command is still stuck
554 * in DISPATCH and you need to do something about it. */
555 if (status & 0x001) {
556 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
557 if (!ustatus && display) {
558 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
559 }
560
561 /* Known to be triggered by screwed up NOTIFY and COND... */
562 if (ustatus & 0x00000001) {
563 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
564 nv_wr32(dev, 0x400500, 0);
565 if (nv_rd32(dev, 0x400808) & 0x80000000) {
566 if (display) {
567 if (nouveau_graph_trapped_channel(dev, &trap.channel))
568 trap.channel = -1;
569 trap.class = nv_rd32(dev, 0x400814);
570 trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
571 trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
572 trap.data = nv_rd32(dev, 0x40080c);
573 trap.data2 = nv_rd32(dev, 0x400810);
574 nouveau_graph_dump_trap_info(dev,
575 "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
576 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
577 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
578 }
579 nv_wr32(dev, 0x400808, 0);
580 } else if (display) {
581 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
582 }
583 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
584 nv_wr32(dev, 0x400848, 0);
585 ustatus &= ~0x00000001;
586 }
587 if (ustatus & 0x00000002) {
588 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
589 nv_wr32(dev, 0x400500, 0);
590 if (nv_rd32(dev, 0x40084c) & 0x80000000) {
591 if (display) {
592 if (nouveau_graph_trapped_channel(dev, &trap.channel))
593 trap.channel = -1;
594 trap.class = nv_rd32(dev, 0x400814);
595 trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
596 trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
597 trap.data = nv_rd32(dev, 0x40085c);
598 trap.data2 = 0;
599 nouveau_graph_dump_trap_info(dev,
600 "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
601 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
602 }
603 nv_wr32(dev, 0x40084c, 0);
604 } else if (display) {
605 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
606 }
607 ustatus &= ~0x00000002;
608 }
609 if (ustatus && display)
610 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
611 nv_wr32(dev, 0x400804, 0xc0000000);
612 nv_wr32(dev, 0x400108, 0x001);
613 status &= ~0x001;
614 }
615
616 /* TRAPs other than dispatch use the "normal" trap regs. */
617 if (status && display) {
618 nouveau_graph_trap_info(dev, &trap);
619 nouveau_graph_dump_trap_info(dev,
620 "PGRAPH_TRAP", &trap);
621 }
622
623 /* M2MF: Memory to memory copy engine. */
624 if (status & 0x002) {
625 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
626 if (!ustatus && display) {
627 NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
628 }
629 if (ustatus & 0x00000001) {
630 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
631 ustatus &= ~0x00000001;
632 }
633 if (ustatus & 0x00000002) {
634 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
635 ustatus &= ~0x00000002;
636 }
637 if (ustatus & 0x00000004) {
638 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
639 ustatus &= ~0x00000004;
640 }
641 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
642 nv_rd32(dev, 0x406804),
643 nv_rd32(dev, 0x406808),
644 nv_rd32(dev, 0x40680c),
645 nv_rd32(dev, 0x406810));
646 if (ustatus && display)
647 NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
648 /* No sane way found yet -- just reset the bugger. */
649 nv_wr32(dev, 0x400040, 2);
650 nv_wr32(dev, 0x400040, 0);
651 nv_wr32(dev, 0x406800, 0xc0000000);
652 nv_wr32(dev, 0x400108, 0x002);
653 status &= ~0x002;
654 }
655
656 /* VFETCH: Fetches data from vertex buffers. */
657 if (status & 0x004) {
658 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
659 if (!ustatus && display) {
660 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
661 }
662 if (ustatus & 0x00000001) {
663 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
664 NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
665 nv_rd32(dev, 0x400c00),
666 nv_rd32(dev, 0x400c08),
667 nv_rd32(dev, 0x400c0c),
668 nv_rd32(dev, 0x400c10));
669 ustatus &= ~0x00000001;
670 }
671 if (ustatus && display)
672 NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
673 nv_wr32(dev, 0x400c04, 0xc0000000);
674 nv_wr32(dev, 0x400108, 0x004);
675 status &= ~0x004;
676 }
677
678 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
679 if (status & 0x008) {
680 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
681 if (!ustatus && display) {
682 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
683 }
684 if (ustatus & 0x00000001) {
685 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
686 NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
687 nv_rd32(dev, 0x401804),
688 nv_rd32(dev, 0x401808),
689 nv_rd32(dev, 0x40180c),
690 nv_rd32(dev, 0x401810));
691 ustatus &= ~0x00000001;
692 }
693 if (ustatus && display)
694 NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
695 /* No sane way found yet -- just reset the bugger. */
696 nv_wr32(dev, 0x400040, 0x80);
697 nv_wr32(dev, 0x400040, 0);
698 nv_wr32(dev, 0x401800, 0xc0000000);
699 nv_wr32(dev, 0x400108, 0x008);
700 status &= ~0x008;
701 }
702
703 /* CCACHE: Handles code and c[] caches and fills them. */
704 if (status & 0x010) {
705 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
706 if (!ustatus && display) {
707 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
708 }
709 if (ustatus & 0x00000001) {
710 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
711 NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
712 nv_rd32(dev, 0x405800),
713 nv_rd32(dev, 0x405804),
714 nv_rd32(dev, 0x405808),
715 nv_rd32(dev, 0x40580c),
716 nv_rd32(dev, 0x405810),
717 nv_rd32(dev, 0x405814),
718 nv_rd32(dev, 0x40581c));
719 ustatus &= ~0x00000001;
720 }
721 if (ustatus && display)
722 NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
723 nv_wr32(dev, 0x405018, 0xc0000000);
724 nv_wr32(dev, 0x400108, 0x010);
725 status &= ~0x010;
726 }
727
728 /* Unknown, not seen yet... 0x402000 is the only trap status reg
729 * remaining, so try to handle it anyway. Perhaps related to that
730 * unknown DMA slot on tesla? */
731 if (status & 0x20) {
732 nv50_fb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
733 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
734 if (display)
735 NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
736 nv_wr32(dev, 0x402000, 0xc0000000);
737 /* no status modifiction on purpose */
738 }
739
740 /* TEXTURE: CUDA texturing units */
741 if (status & 0x040) {
742 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
743 "PGRAPH_TRAP_TEXTURE");
744 nv_wr32(dev, 0x400108, 0x040);
745 status &= ~0x040;
746 }
747
748 /* MP: CUDA execution engines. */
749 if (status & 0x080) {
750 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
751 "PGRAPH_TRAP_MP");
752 nv_wr32(dev, 0x400108, 0x080);
753 status &= ~0x080;
754 }
755
756 /* TPDMA: Handles TP-initiated uncached memory accesses:
757 * l[], g[], stack, 2d surfaces, render targets. */
758 if (status & 0x100) {
759 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
760 "PGRAPH_TRAP_TPDMA");
761 nv_wr32(dev, 0x400108, 0x100);
762 status &= ~0x100;
763 }
764
765 if (status) {
766 if (display)
767 NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
768 status);
769 nv_wr32(dev, 0x400108, status);
770 }
771}
772
773/* There must be a *lot* of these. Will take some time to gather them up. */
774static struct nouveau_enum nv50_data_error_names[] =
775{
776 { 4, "INVALID_VALUE" },
777 { 5, "INVALID_ENUM" },
778 { 8, "INVALID_OBJECT" },
779 { 0xc, "INVALID_BITFIELD" },
780 { 0x28, "MP_NO_REG_SPACE" },
781 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
782 {}
783};
784
785static void
786nv50_pgraph_irq_handler(struct drm_device *dev)
787{
788 struct nouveau_pgraph_trap trap;
789 int unhandled = 0;
790 uint32_t status;
791
792 while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
793 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
794 if (status & 0x00000001) {
795 nouveau_graph_trap_info(dev, &trap);
796 if (nouveau_ratelimit())
797 nouveau_graph_dump_trap_info(dev,
798 "PGRAPH_NOTIFY", &trap);
799 status &= ~0x00000001;
800 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
801 }
802
803 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
804 * when you write 0x200 to 0x50c0 method 0x31c. */
805 if (status & 0x00000002) {
806 nouveau_graph_trap_info(dev, &trap);
807 if (nouveau_ratelimit())
808 nouveau_graph_dump_trap_info(dev,
809 "PGRAPH_COMPUTE_QUERY", &trap);
810 status &= ~0x00000002;
811 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
812 }
813
814 /* Unknown, never seen: 0x4 */
815
816 /* ILLEGAL_MTHD: You used a wrong method for this class. */
817 if (status & 0x00000010) {
818 nouveau_graph_trap_info(dev, &trap);
819 if (nouveau_pgraph_intr_swmthd(dev, &trap))
820 unhandled = 1;
821 if (unhandled && nouveau_ratelimit())
822 nouveau_graph_dump_trap_info(dev,
823 "PGRAPH_ILLEGAL_MTHD", &trap);
824 status &= ~0x00000010;
825 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
826 }
827
828 /* ILLEGAL_CLASS: You used a wrong class. */
829 if (status & 0x00000020) {
830 nouveau_graph_trap_info(dev, &trap);
831 if (nouveau_ratelimit())
832 nouveau_graph_dump_trap_info(dev,
833 "PGRAPH_ILLEGAL_CLASS", &trap);
834 status &= ~0x00000020;
835 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
836 }
837
838 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
839 if (status & 0x00000040) {
840 nouveau_graph_trap_info(dev, &trap);
841 if (nouveau_ratelimit())
842 nouveau_graph_dump_trap_info(dev,
843 "PGRAPH_DOUBLE_NOTIFY", &trap);
844 status &= ~0x00000040;
845 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
846 }
847
848 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
849 if (status & 0x00001000) {
850 nv_wr32(dev, 0x400500, 0x00000000);
851 nv_wr32(dev, NV03_PGRAPH_INTR,
852 NV_PGRAPH_INTR_CONTEXT_SWITCH);
853 nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
854 NV40_PGRAPH_INTR_EN) &
855 ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
856 nv_wr32(dev, 0x400500, 0x00010001);
857
858 nv50_graph_context_switch(dev);
859
860 status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
861 }
862
863 /* BUFFER_NOTIFY: Your m2mf transfer finished */
864 if (status & 0x00010000) {
865 nouveau_graph_trap_info(dev, &trap);
866 if (nouveau_ratelimit())
867 nouveau_graph_dump_trap_info(dev,
868 "PGRAPH_BUFFER_NOTIFY", &trap);
869 status &= ~0x00010000;
870 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
871 }
872
873 /* DATA_ERROR: Invalid value for this method, or invalid
874 * state in current PGRAPH context for this operation */
875 if (status & 0x00100000) {
876 nouveau_graph_trap_info(dev, &trap);
877 if (nouveau_ratelimit()) {
878 nouveau_graph_dump_trap_info(dev,
879 "PGRAPH_DATA_ERROR", &trap);
880 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
881 nouveau_enum_print(nv50_data_error_names,
882 nv_rd32(dev, 0x400110));
883 printk("\n");
884 }
885 status &= ~0x00100000;
886 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
887 }
888
889 /* TRAP: Something bad happened in the middle of command
890 * execution. Has a billion types, subtypes, and even
891 * subsubtypes. */
892 if (status & 0x00200000) {
893 nv50_pgraph_trap_handler(dev);
894 status &= ~0x00200000;
895 nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
896 }
897
898 /* Unknown, never seen: 0x00400000 */
899
900 /* SINGLE_STEP: Happens on every method if you turned on
901 * single stepping in 40008c */
902 if (status & 0x01000000) {
903 nouveau_graph_trap_info(dev, &trap);
904 if (nouveau_ratelimit())
905 nouveau_graph_dump_trap_info(dev,
906 "PGRAPH_SINGLE_STEP", &trap);
907 status &= ~0x01000000;
908 nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
909 }
910
911 /* 0x02000000 happens when you pause a ctxprog...
912 * but the only way this can happen that I know is by
913 * poking the relevant MMIO register, and we don't
914 * do that. */
915
916 if (status) {
917 NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
918 status);
919 nv_wr32(dev, NV03_PGRAPH_INTR, status);
920 }
921
922 {
923 const int isb = (1 << 16) | (1 << 0);
924
925 if ((nv_rd32(dev, 0x400500) & isb) != isb)
926 nv_wr32(dev, 0x400500,
927 nv_rd32(dev, 0x400500) | isb);
928 }
929 }
930
931 nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
932 if (nv_rd32(dev, 0x400824) & (1 << 31))
933 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
934}
935
936irqreturn_t 72irqreturn_t
937nouveau_irq_handler(DRM_IRQ_ARGS) 73nouveau_irq_handler(DRM_IRQ_ARGS)
938{ 74{
939 struct drm_device *dev = (struct drm_device *)arg; 75 struct drm_device *dev = (struct drm_device *)arg;
940 struct drm_nouveau_private *dev_priv = dev->dev_private; 76 struct drm_nouveau_private *dev_priv = dev->dev_private;
941 unsigned long flags; 77 unsigned long flags;
942 u32 status; 78 u32 stat;
943 int i; 79 int i;
944 80
945 status = nv_rd32(dev, NV03_PMC_INTR_0); 81 stat = nv_rd32(dev, NV03_PMC_INTR_0);
946 if (!status) 82 if (!stat)
947 return IRQ_NONE; 83 return IRQ_NONE;
948 84
949 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 85 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
950 86 for (i = 0; i < 32 && stat; i++) {
951 if (status & NV_PMC_INTR_0_PGRAPH_PENDING) { 87 if (!(stat & (1 << i)) || !dev_priv->irq_handler[i])
952 if (dev_priv->card_type >= NV_50)
953 nv50_pgraph_irq_handler(dev);
954 else
955 nouveau_pgraph_irq_handler(dev);
956
957 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
958 }
959
960 for (i = 0; i < 32 && status; i++) {
961 if (!(status & (1 << i)) || !dev_priv->irq_handler[i])
962 continue; 88 continue;
963 89
964 dev_priv->irq_handler[i](dev); 90 dev_priv->irq_handler[i](dev);
965 status &= ~(1 << i); 91 stat &= ~(1 << i);
966 } 92 }
967 93
968 if (status)
969 NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);
970
971 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
972
973 if (dev_priv->msi_enabled) 94 if (dev_priv->msi_enabled)
974 nv_wr08(dev, 0x00088068, 0xff); 95 nv_wr08(dev, 0x00088068, 0xff);
96 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
975 97
98 if (stat && nouveau_ratelimit())
99 NV_ERROR(dev, "PMC - unhandled INTR 0x%08x\n", stat);
976 return IRQ_HANDLED; 100 return IRQ_HANDLED;
977} 101}
978 102
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 54078186fe65..94429553433c 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -113,6 +113,24 @@ nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
113 return -ENOENT; 113 return -ENOENT;
114} 114}
115 115
116int
117nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
118 u32 class, u32 mthd, u32 data)
119{
120 struct drm_nouveau_private *dev_priv = dev->dev_private;
121 struct nouveau_channel *chan = NULL;
122 unsigned long flags;
123 int ret = -EINVAL;
124
125 spin_lock_irqsave(&dev_priv->channels.lock, flags);
126 if (chid > 0 && chid < dev_priv->engine.fifo.channels)
127 chan = dev_priv->channels.ptr[chid];
128 if (chan)
129 ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
130 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
131 return ret;
132}
133
116/* NVidia uses context objects to drive drawing operations. 134/* NVidia uses context objects to drive drawing operations.
117 135
118 Context objects can be selected into 8 subchannels in the FIFO, 136 Context objects can be selected into 8 subchannels in the FIFO,
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index 239519aefce6..0bc616d35eb6 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -27,8 +27,10 @@
27#include "nouveau_drm.h" 27#include "nouveau_drm.h"
28#include "nouveau_drv.h" 28#include "nouveau_drv.h"
29#include "nouveau_hw.h" 29#include "nouveau_hw.h"
30#include "nouveau_util.h"
30 31
31static int nv04_graph_register(struct drm_device *dev); 32static int nv04_graph_register(struct drm_device *dev);
33static void nv04_graph_isr(struct drm_device *dev);
32 34
33static uint32_t nv04_graph_ctx_regs[] = { 35static uint32_t nv04_graph_ctx_regs[] = {
34 0x0040053c, 36 0x0040053c,
@@ -363,7 +365,7 @@ nv04_graph_channel(struct drm_device *dev)
363 return dev_priv->channels.ptr[chid]; 365 return dev_priv->channels.ptr[chid];
364} 366}
365 367
366void 368static void
367nv04_graph_context_switch(struct drm_device *dev) 369nv04_graph_context_switch(struct drm_device *dev)
368{ 370{
369 struct drm_nouveau_private *dev_priv = dev->dev_private; 371 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -498,6 +500,7 @@ int nv04_graph_init(struct drm_device *dev)
498 return ret; 500 return ret;
499 501
500 /* Enable PGRAPH interrupts */ 502 /* Enable PGRAPH interrupts */
503 nouveau_irq_register(dev, 12, nv04_graph_isr);
501 nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF); 504 nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
502 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 505 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
503 506
@@ -533,6 +536,8 @@ int nv04_graph_init(struct drm_device *dev)
533 536
534void nv04_graph_takedown(struct drm_device *dev) 537void nv04_graph_takedown(struct drm_device *dev)
535{ 538{
539 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
540 nouveau_irq_unregister(dev, 12);
536} 541}
537 542
538void 543void
@@ -1224,3 +1229,89 @@ nv04_graph_register(struct drm_device *dev)
1224 dev_priv->engine.graph.registered = true; 1229 dev_priv->engine.graph.registered = true;
1225 return 0; 1230 return 0;
1226}; 1231};
1232
1233static struct nouveau_bitfield nv04_graph_intr[] = {
1234 { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
1235 {}
1236};
1237
1238static struct nouveau_bitfield nv04_graph_nstatus[] =
1239{
1240 { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
1241 { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
1242 { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
1243 { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
1244 {}
1245};
1246
1247struct nouveau_bitfield nv04_graph_nsource[] =
1248{
1249 { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
1250 { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
1251 { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
1252 { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
1253 { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
1254 { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
1255 { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
1256 { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
1257 { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
1258 { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
1259 { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
1260 { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
1261 { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
1262 { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
1263 { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
1264 { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
1265 { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
1266 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
1267 { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
1268 {}
1269};
1270
1271static void
1272nv04_graph_isr(struct drm_device *dev)
1273{
1274 u32 stat;
1275
1276 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1277 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
1278 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
1279 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1280 u32 chid = (addr & 0x0f000000) >> 24;
1281 u32 subc = (addr & 0x0000e000) >> 13;
1282 u32 mthd = (addr & 0x00001ffc);
1283 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1284 u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
1285 u32 show = stat;
1286
1287 if (stat & NV_PGRAPH_INTR_NOTIFY) {
1288 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
1289 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
1290 show &= ~NV_PGRAPH_INTR_NOTIFY;
1291 }
1292 }
1293
1294 if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
1295 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
1296 stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1297 show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1298 nv04_graph_context_switch(dev);
1299 }
1300
1301 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
1302 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
1303
1304 if (show && nouveau_ratelimit()) {
1305 NV_INFO(dev, "PGRAPH -");
1306 nouveau_bitfield_print(nv04_graph_intr, show);
1307 printk(" nsource:");
1308 nouveau_bitfield_print(nv04_graph_nsource, nsource);
1309 printk(" nstatus:");
1310 nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
1311 printk("\n");
1312 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
1313 "mthd 0x%04x data 0x%08x\n",
1314 chid, subc, class, mthd, data);
1315 }
1316 }
1317}
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 1cd141edca04..536b39e4a9e2 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -26,8 +26,10 @@
26#include "drm.h" 26#include "drm.h"
27#include "nouveau_drm.h" 27#include "nouveau_drm.h"
28#include "nouveau_drv.h" 28#include "nouveau_drv.h"
29#include "nouveau_util.h"
29 30
30static int nv10_graph_register(struct drm_device *); 31static int nv10_graph_register(struct drm_device *);
32static void nv10_graph_isr(struct drm_device *);
31 33
32#define NV10_FIFO_NUMBER 32 34#define NV10_FIFO_NUMBER 32
33 35
@@ -788,7 +790,7 @@ nv10_graph_unload_context(struct drm_device *dev)
788 return 0; 790 return 0;
789} 791}
790 792
791void 793static void
792nv10_graph_context_switch(struct drm_device *dev) 794nv10_graph_context_switch(struct drm_device *dev)
793{ 795{
794 struct drm_nouveau_private *dev_priv = dev->dev_private; 796 struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -924,6 +926,7 @@ int nv10_graph_init(struct drm_device *dev)
924 if (ret) 926 if (ret)
925 return ret; 927 return ret;
926 928
929 nouveau_irq_register(dev, 12, nv10_graph_isr);
927 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 930 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
928 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 931 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
929 932
@@ -966,6 +969,8 @@ int nv10_graph_init(struct drm_device *dev)
966 969
967void nv10_graph_takedown(struct drm_device *dev) 970void nv10_graph_takedown(struct drm_device *dev)
968{ 971{
972 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
973 nouveau_irq_unregister(dev, 12);
969} 974}
970 975
971static int 976static int
@@ -1117,3 +1122,66 @@ nv10_graph_register(struct drm_device *dev)
1117 dev_priv->engine.graph.registered = true; 1122 dev_priv->engine.graph.registered = true;
1118 return 0; 1123 return 0;
1119} 1124}
1125
1126struct nouveau_bitfield nv10_graph_intr[] = {
1127 { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
1128 { NV_PGRAPH_INTR_ERROR, "ERROR" },
1129 {}
1130};
1131
1132struct nouveau_bitfield nv10_graph_nstatus[] =
1133{
1134 { NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
1135 { NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
1136 { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
1137 { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
1138 {}
1139};
1140
1141static void
1142nv10_graph_isr(struct drm_device *dev)
1143{
1144 u32 stat;
1145
1146 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1147 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
1148 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
1149 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
1150 u32 chid = (addr & 0x01f00000) >> 20;
1151 u32 subc = (addr & 0x00070000) >> 16;
1152 u32 mthd = (addr & 0x00001ffc);
1153 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
1154 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
1155 u32 show = stat;
1156
1157 if (stat & NV_PGRAPH_INTR_ERROR) {
1158 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
1159 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
1160 show &= ~NV_PGRAPH_INTR_ERROR;
1161 }
1162 }
1163
1164 if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
1165 nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
1166 stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1167 show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1168 nv10_graph_context_switch(dev);
1169 }
1170
1171 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
1172 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
1173
1174 if (show && nouveau_ratelimit()) {
1175 NV_INFO(dev, "PGRAPH -");
1176 nouveau_bitfield_print(nv10_graph_intr, show);
1177 printk(" nsource:");
1178 nouveau_bitfield_print(nv04_graph_nsource, nsource);
1179 printk(" nstatus:");
1180 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
1181 printk("\n");
1182 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
1183 "mthd 0x%04x data 0x%08x\n",
1184 chid, subc, class, mthd, data);
1185 }
1186 }
1187}
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index bd065c2fcba4..8464b76798d5 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -34,6 +34,7 @@
34 34
35static int nv20_graph_register(struct drm_device *); 35static int nv20_graph_register(struct drm_device *);
36static int nv30_graph_register(struct drm_device *); 36static int nv30_graph_register(struct drm_device *);
37static void nv20_graph_isr(struct drm_device *);
37 38
38static void 39static void
39nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx) 40nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
@@ -584,6 +585,7 @@ nv20_graph_init(struct drm_device *dev)
584 return ret; 585 return ret;
585 } 586 }
586 587
588 nouveau_irq_register(dev, 12, nv20_graph_isr);
587 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 589 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
588 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 590 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
589 591
@@ -661,6 +663,9 @@ nv20_graph_takedown(struct drm_device *dev)
661 struct drm_nouveau_private *dev_priv = dev->dev_private; 663 struct drm_nouveau_private *dev_priv = dev->dev_private;
662 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 664 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
663 665
666 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
667 nouveau_irq_unregister(dev, 12);
668
664 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table); 669 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
665} 670}
666 671
@@ -712,6 +717,7 @@ nv30_graph_init(struct drm_device *dev)
712 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, 717 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
713 pgraph->ctx_table->pinst >> 4); 718 pgraph->ctx_table->pinst >> 4);
714 719
720 nouveau_irq_register(dev, 12, nv20_graph_isr);
715 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 721 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
716 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 722 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
717 723
@@ -850,3 +856,44 @@ nv30_graph_register(struct drm_device *dev)
850 dev_priv->engine.graph.registered = true; 856 dev_priv->engine.graph.registered = true;
851 return 0; 857 return 0;
852} 858}
859
860static void
861nv20_graph_isr(struct drm_device *dev)
862{
863 u32 stat;
864
865 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
866 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
867 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
868 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
869 u32 chid = (addr & 0x01f00000) >> 20;
870 u32 subc = (addr & 0x00070000) >> 16;
871 u32 mthd = (addr & 0x00001ffc);
872 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
873 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xfff;
874 u32 show = stat;
875
876 if (stat & NV_PGRAPH_INTR_ERROR) {
877 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
878 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
879 show &= ~NV_PGRAPH_INTR_ERROR;
880 }
881 }
882
883 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
884 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
885
886 if (show && nouveau_ratelimit()) {
887 NV_INFO(dev, "PGRAPH -");
888 nouveau_bitfield_print(nv10_graph_intr, show);
889 printk(" nsource:");
890 nouveau_bitfield_print(nv04_graph_nsource, nsource);
891 printk(" nstatus:");
892 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
893 printk("\n");
894 NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
895 "mthd 0x%04x data 0x%08x\n",
896 chid, subc, class, mthd, data);
897 }
898 }
899}
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 7a51608b55ba..0618846a97ce 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -30,6 +30,7 @@
30#include "nouveau_grctx.h" 30#include "nouveau_grctx.h"
31 31
32static int nv40_graph_register(struct drm_device *); 32static int nv40_graph_register(struct drm_device *);
33static void nv40_graph_isr(struct drm_device *);
33 34
34struct nouveau_channel * 35struct nouveau_channel *
35nv40_graph_channel(struct drm_device *dev) 36nv40_graph_channel(struct drm_device *dev)
@@ -277,6 +278,7 @@ nv40_graph_init(struct drm_device *dev)
277 /* No context present currently */ 278 /* No context present currently */
278 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); 279 nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
279 280
281 nouveau_irq_register(dev, 12, nv40_graph_isr);
280 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 282 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
281 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); 283 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
282 284
@@ -408,6 +410,7 @@ nv40_graph_init(struct drm_device *dev)
408 410
409void nv40_graph_takedown(struct drm_device *dev) 411void nv40_graph_takedown(struct drm_device *dev)
410{ 412{
413 nouveau_irq_unregister(dev, 12);
411} 414}
412 415
413static int 416static int
@@ -449,3 +452,69 @@ nv40_graph_register(struct drm_device *dev)
449 dev_priv->engine.graph.registered = true; 452 dev_priv->engine.graph.registered = true;
450 return 0; 453 return 0;
451} 454}
455
456static int
457nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
458{
459 struct drm_nouveau_private *dev_priv = dev->dev_private;
460 struct nouveau_channel *chan;
461 unsigned long flags;
462 int i;
463
464 spin_lock_irqsave(&dev_priv->channels.lock, flags);
465 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
466 chan = dev_priv->channels.ptr[i];
467 if (!chan || !chan->ramin_grctx)
468 continue;
469
470 if (inst == chan->ramin_grctx->pinst)
471 break;
472 }
473 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
474 return i;
475}
476
477static void
478nv40_graph_isr(struct drm_device *dev)
479{
480 u32 stat;
481
482 while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
483 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
484 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
485 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
486 u32 chid = nv40_graph_isr_chid(dev, inst);
487 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
488 u32 subc = (addr & 0x00070000) >> 16;
489 u32 mthd = (addr & 0x00001ffc);
490 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
491 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
492 u32 show = stat;
493
494 if (stat & NV_PGRAPH_INTR_ERROR) {
495 if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
496 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
497 show &= ~NV_PGRAPH_INTR_ERROR;
498 } else
499 if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
500 nv_mask(dev, 0x402000, 0, 0);
501 }
502 }
503
504 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
505 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
506
507 if (show && nouveau_ratelimit()) {
508 NV_INFO(dev, "PGRAPH -");
509 nouveau_bitfield_print(nv10_graph_intr, show);
510 printk(" nsource:");
511 nouveau_bitfield_print(nv04_graph_nsource, nsource);
512 printk(" nstatus:");
513 nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
514 printk("\n");
515 NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
516 "class 0x%04x mthd 0x%04x data 0x%08x\n",
517 chid, inst, subc, class, mthd, data);
518 }
519 }
520}
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index 6785269f778a..b3900788c66d 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -32,7 +32,8 @@
32#include "nouveau_dma.h" 32#include "nouveau_dma.h"
33#include "nv50_evo.h" 33#include "nv50_evo.h"
34 34
35static int nv50_graph_register(struct drm_device *); 35static int nv50_graph_register(struct drm_device *);
36static void nv50_graph_isr(struct drm_device *);
36 37
37static void 38static void
38nv50_graph_init_reset(struct drm_device *dev) 39nv50_graph_init_reset(struct drm_device *dev)
@@ -50,6 +51,7 @@ nv50_graph_init_intr(struct drm_device *dev)
50{ 51{
51 NV_DEBUG(dev, "\n"); 52 NV_DEBUG(dev, "\n");
52 53
54 nouveau_irq_register(dev, 12, nv50_graph_isr);
53 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff); 55 nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
54 nv_wr32(dev, 0x400138, 0xffffffff); 56 nv_wr32(dev, 0x400138, 0xffffffff);
55 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff); 57 nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
@@ -165,6 +167,8 @@ void
165nv50_graph_takedown(struct drm_device *dev) 167nv50_graph_takedown(struct drm_device *dev)
166{ 168{
167 NV_DEBUG(dev, "\n"); 169 NV_DEBUG(dev, "\n");
170 nv_wr32(dev, 0x40013c, 0x00000000);
171 nouveau_irq_unregister(dev, 12);
168} 172}
169 173
170void 174void
@@ -324,7 +328,7 @@ nv50_graph_unload_context(struct drm_device *dev)
324 return 0; 328 return 0;
325} 329}
326 330
327void 331static void
328nv50_graph_context_switch(struct drm_device *dev) 332nv50_graph_context_switch(struct drm_device *dev)
329{ 333{
330 uint32_t inst; 334 uint32_t inst;
@@ -512,3 +516,495 @@ nv86_graph_tlb_flush(struct drm_device *dev)
512 nv_mask(dev, 0x400500, 0x00000001, 0x00000001); 516 nv_mask(dev, 0x400500, 0x00000001, 0x00000001);
513 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 517 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
514} 518}
519
520static struct nouveau_enum nv50_mp_exec_error_names[] =
521{
522 { 3, "STACK_UNDERFLOW" },
523 { 4, "QUADON_ACTIVE" },
524 { 8, "TIMEOUT" },
525 { 0x10, "INVALID_OPCODE" },
526 { 0x40, "BREAKPOINT" },
527 {}
528};
529
530static struct nouveau_bitfield nv50_graph_trap_m2mf[] = {
531 { 0x00000001, "NOTIFY" },
532 { 0x00000002, "IN" },
533 { 0x00000004, "OUT" },
534 {}
535};
536
537static struct nouveau_bitfield nv50_graph_trap_vfetch[] = {
538 { 0x00000001, "FAULT" },
539 {}
540};
541
542static struct nouveau_bitfield nv50_graph_trap_strmout[] = {
543 { 0x00000001, "FAULT" },
544 {}
545};
546
547static struct nouveau_bitfield nv50_graph_trap_ccache[] = {
548 { 0x00000001, "FAULT" },
549 {}
550};
551
552/* There must be a *lot* of these. Will take some time to gather them up. */
553static struct nouveau_enum nv50_data_error_names[] = {
554 { 4, "INVALID_VALUE" },
555 { 5, "INVALID_ENUM" },
556 { 8, "INVALID_OBJECT" },
557 { 0xc, "INVALID_BITFIELD" },
558 { 0x28, "MP_NO_REG_SPACE" },
559 { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
560 {}
561};
562
563static struct nouveau_bitfield nv50_graph_intr[] = {
564 { 0x00000001, "NOTIFY" },
565 { 0x00000002, "COMPUTE_QUERY" },
566 { 0x00000010, "ILLEGAL_MTHD" },
567 { 0x00000020, "ILLEGAL_CLASS" },
568 { 0x00000040, "DOUBLE_NOTIFY" },
569 { 0x00001000, "CONTEXT_SWITCH" },
570 { 0x00010000, "BUFFER_NOTIFY" },
571 { 0x00100000, "DATA_ERROR" },
572 { 0x00200000, "TRAP" },
573 { 0x01000000, "SINGLE_STEP" },
574 {}
575};
576
577static void
578nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
579{
580 struct drm_nouveau_private *dev_priv = dev->dev_private;
581 uint32_t units = nv_rd32(dev, 0x1540);
582 uint32_t addr, mp10, status, pc, oplow, ophigh;
583 int i;
584 int mps = 0;
585 for (i = 0; i < 4; i++) {
586 if (!(units & 1 << (i+24)))
587 continue;
588 if (dev_priv->chipset < 0xa0)
589 addr = 0x408200 + (tpid << 12) + (i << 7);
590 else
591 addr = 0x408100 + (tpid << 11) + (i << 7);
592 mp10 = nv_rd32(dev, addr + 0x10);
593 status = nv_rd32(dev, addr + 0x14);
594 if (!status)
595 continue;
596 if (display) {
597 nv_rd32(dev, addr + 0x20);
598 pc = nv_rd32(dev, addr + 0x24);
599 oplow = nv_rd32(dev, addr + 0x70);
600 ophigh= nv_rd32(dev, addr + 0x74);
601 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
602 "TP %d MP %d: ", tpid, i);
603 nouveau_enum_print(nv50_mp_exec_error_names, status);
604 printk(" at %06x warp %d, opcode %08x %08x\n",
605 pc&0xffffff, pc >> 24,
606 oplow, ophigh);
607 }
608 nv_wr32(dev, addr + 0x10, mp10);
609 nv_wr32(dev, addr + 0x14, 0);
610 mps++;
611 }
612 if (!mps && display)
613 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
614 "No MPs claiming errors?\n", tpid);
615}
616
617static void
618nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
619 uint32_t ustatus_new, int display, const char *name)
620{
621 struct drm_nouveau_private *dev_priv = dev->dev_private;
622 int tps = 0;
623 uint32_t units = nv_rd32(dev, 0x1540);
624 int i, r;
625 uint32_t ustatus_addr, ustatus;
626 for (i = 0; i < 16; i++) {
627 if (!(units & (1 << i)))
628 continue;
629 if (dev_priv->chipset < 0xa0)
630 ustatus_addr = ustatus_old + (i << 12);
631 else
632 ustatus_addr = ustatus_new + (i << 11);
633 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
634 if (!ustatus)
635 continue;
636 tps++;
637 switch (type) {
638 case 6: /* texture error... unknown for now */
639 nv50_fb_vm_trap(dev, display, name);
640 if (display) {
641 NV_ERROR(dev, "magic set %d:\n", i);
642 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
643 NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
644 nv_rd32(dev, r));
645 }
646 break;
647 case 7: /* MP error */
648 if (ustatus & 0x00010000) {
649 nv50_pgraph_mp_trap(dev, i, display);
650 ustatus &= ~0x00010000;
651 }
652 break;
653 case 8: /* TPDMA error */
654 {
655 uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
656 uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
657 uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
658 uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
659 uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
660 uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
661 uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
662 nv50_fb_vm_trap(dev, display, name);
663 /* 2d engine destination */
664 if (ustatus & 0x00000010) {
665 if (display) {
666 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
667 i, e14, e10);
668 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
669 i, e0c, e18, e1c, e20, e24);
670 }
671 ustatus &= ~0x00000010;
672 }
673 /* Render target */
674 if (ustatus & 0x00000040) {
675 if (display) {
676 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
677 i, e14, e10);
678 NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
679 i, e0c, e18, e1c, e20, e24);
680 }
681 ustatus &= ~0x00000040;
682 }
683 /* CUDA memory: l[], g[] or stack. */
684 if (ustatus & 0x00000080) {
685 if (display) {
686 if (e18 & 0x80000000) {
687 /* g[] read fault? */
688 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
689 i, e14, e10 | ((e18 >> 24) & 0x1f));
690 e18 &= ~0x1f000000;
691 } else if (e18 & 0xc) {
692 /* g[] write fault? */
693 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
694 i, e14, e10 | ((e18 >> 7) & 0x1f));
695 e18 &= ~0x00000f80;
696 } else {
697 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
698 i, e14, e10);
699 }
700 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
701 i, e0c, e18, e1c, e20, e24);
702 }
703 ustatus &= ~0x00000080;
704 }
705 }
706 break;
707 }
708 if (ustatus) {
709 if (display)
710 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
711 }
712 nv_wr32(dev, ustatus_addr, 0xc0000000);
713 }
714
715 if (!tps && display)
716 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
717}
718
719static int
720nv50_pgraph_trap_handler(struct drm_device *dev, u32 display, u64 inst, u32 chid)
721{
722 u32 status = nv_rd32(dev, 0x400108);
723 u32 ustatus;
724
725 if (!status && display) {
726 NV_INFO(dev, "PGRAPH - TRAP: no units reporting traps?\n");
727 return 1;
728 }
729
730 /* DISPATCH: Relays commands to other units and handles NOTIFY,
731 * COND, QUERY. If you get a trap from it, the command is still stuck
732 * in DISPATCH and you need to do something about it. */
733 if (status & 0x001) {
734 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
735 if (!ustatus && display) {
736 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
737 }
738
739 nv_wr32(dev, 0x400500, 0x00000000);
740
741 /* Known to be triggered by screwed up NOTIFY and COND... */
742 if (ustatus & 0x00000001) {
743 u32 addr = nv_rd32(dev, 0x400808);
744 u32 subc = (addr & 0x00070000) >> 16;
745 u32 mthd = (addr & 0x00001ffc);
746 u32 datal = nv_rd32(dev, 0x40080c);
747 u32 datah = nv_rd32(dev, 0x400810);
748 u32 class = nv_rd32(dev, 0x400814);
749 u32 r848 = nv_rd32(dev, 0x400848);
750
751 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_FAULT\n");
752 if (display && (addr & 0x80000000)) {
753 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
754 "subc %d class 0x%04x mthd 0x%04x "
755 "data 0x%08x%08x "
756 "400808 0x%08x 400848 0x%08x\n",
757 chid, inst, subc, class, mthd, datah,
758 datal, addr, r848);
759 } else
760 if (display) {
761 NV_INFO(dev, "PGRAPH - no stuck command?\n");
762 }
763
764 nv_wr32(dev, 0x400808, 0);
765 nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
766 nv_wr32(dev, 0x400848, 0);
767 ustatus &= ~0x00000001;
768 }
769
770 if (ustatus & 0x00000002) {
771 u32 addr = nv_rd32(dev, 0x40084c);
772 u32 subc = (addr & 0x00070000) >> 16;
773 u32 mthd = (addr & 0x00001ffc);
774 u32 data = nv_rd32(dev, 0x40085c);
775 u32 class = nv_rd32(dev, 0x400814);
776
777 NV_INFO(dev, "PGRAPH - TRAP DISPATCH_QUERY\n");
778 if (display && (addr & 0x80000000)) {
779 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) "
780 "subc %d class 0x%04x mthd 0x%04x "
781 "data 0x%08x 40084c 0x%08x\n",
782 chid, inst, subc, class, mthd,
783 data, addr);
784 } else
785 if (display) {
786 NV_INFO(dev, "PGRAPH - no stuck command?\n");
787 }
788
789 nv_wr32(dev, 0x40084c, 0);
790 ustatus &= ~0x00000002;
791 }
792
793 if (ustatus && display) {
794 NV_INFO(dev, "PGRAPH - TRAP_DISPATCH (unknown "
795 "0x%08x)\n", ustatus);
796 }
797
798 nv_wr32(dev, 0x400804, 0xc0000000);
799 nv_wr32(dev, 0x400108, 0x001);
800 status &= ~0x001;
801 if (!status)
802 return 0;
803 }
804
805 /* M2MF: Memory to memory copy engine. */
806 if (status & 0x002) {
807 u32 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
808 if (display) {
809 NV_INFO(dev, "PGRAPH - TRAP_M2MF");
810 nouveau_bitfield_print(nv50_graph_trap_m2mf, ustatus);
811 printk("\n");
812 NV_INFO(dev, "PGRAPH - TRAP_M2MF %08x %08x %08x %08x\n",
813 nv_rd32(dev, 0x406804), nv_rd32(dev, 0x406808),
814 nv_rd32(dev, 0x40680c), nv_rd32(dev, 0x406810));
815
816 }
817
818 /* No sane way found yet -- just reset the bugger. */
819 nv_wr32(dev, 0x400040, 2);
820 nv_wr32(dev, 0x400040, 0);
821 nv_wr32(dev, 0x406800, 0xc0000000);
822 nv_wr32(dev, 0x400108, 0x002);
823 status &= ~0x002;
824 }
825
826 /* VFETCH: Fetches data from vertex buffers. */
827 if (status & 0x004) {
828 u32 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
829 if (display) {
830 NV_INFO(dev, "PGRAPH - TRAP_VFETCH");
831 nouveau_bitfield_print(nv50_graph_trap_vfetch, ustatus);
832 printk("\n");
833 NV_INFO(dev, "PGRAPH - TRAP_VFETCH %08x %08x %08x %08x\n",
834 nv_rd32(dev, 0x400c00), nv_rd32(dev, 0x400c08),
835 nv_rd32(dev, 0x400c0c), nv_rd32(dev, 0x400c10));
836 }
837
838 nv_wr32(dev, 0x400c04, 0xc0000000);
839 nv_wr32(dev, 0x400108, 0x004);
840 status &= ~0x004;
841 }
842
843 /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
844 if (status & 0x008) {
845 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
846 if (display) {
847 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT");
848 nouveau_bitfield_print(nv50_graph_trap_strmout, ustatus);
849 printk("\n");
850 NV_INFO(dev, "PGRAPH - TRAP_STRMOUT %08x %08x %08x %08x\n",
851 nv_rd32(dev, 0x401804), nv_rd32(dev, 0x401808),
852 nv_rd32(dev, 0x40180c), nv_rd32(dev, 0x401810));
853
854 }
855
856 /* No sane way found yet -- just reset the bugger. */
857 nv_wr32(dev, 0x400040, 0x80);
858 nv_wr32(dev, 0x400040, 0);
859 nv_wr32(dev, 0x401800, 0xc0000000);
860 nv_wr32(dev, 0x400108, 0x008);
861 status &= ~0x008;
862 }
863
864 /* CCACHE: Handles code and c[] caches and fills them. */
865 if (status & 0x010) {
866 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
867 if (display) {
868 NV_INFO(dev, "PGRAPH - TRAP_CCACHE");
869 nouveau_bitfield_print(nv50_graph_trap_ccache, ustatus);
870 printk("\n");
871 NV_INFO(dev, "PGRAPH - TRAP_CCACHE %08x %08x %08x %08x"
872 " %08x %08x %08x\n",
873 nv_rd32(dev, 0x405800), nv_rd32(dev, 0x405804),
874 nv_rd32(dev, 0x405808), nv_rd32(dev, 0x40580c),
875 nv_rd32(dev, 0x405810), nv_rd32(dev, 0x405814),
876 nv_rd32(dev, 0x40581c));
877
878 }
879
880 nv_wr32(dev, 0x405018, 0xc0000000);
881 nv_wr32(dev, 0x400108, 0x010);
882 status &= ~0x010;
883 }
884
885 /* Unknown, not seen yet... 0x402000 is the only trap status reg
886 * remaining, so try to handle it anyway. Perhaps related to that
887 * unknown DMA slot on tesla? */
888 if (status & 0x20) {
889 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
890 if (display)
891 NV_INFO(dev, "PGRAPH - TRAP_UNKC04 0x%08x\n", ustatus);
892 nv_wr32(dev, 0x402000, 0xc0000000);
893 /* no status modifiction on purpose */
894 }
895
896 /* TEXTURE: CUDA texturing units */
897 if (status & 0x040) {
898 nv50_pgraph_tp_trap(dev, 6, 0x408900, 0x408600, display,
899 "PGRAPH - TRAP_TEXTURE");
900 nv_wr32(dev, 0x400108, 0x040);
901 status &= ~0x040;
902 }
903
904 /* MP: CUDA execution engines. */
905 if (status & 0x080) {
906 nv50_pgraph_tp_trap(dev, 7, 0x408314, 0x40831c, display,
907 "PGRAPH - TRAP_MP");
908 nv_wr32(dev, 0x400108, 0x080);
909 status &= ~0x080;
910 }
911
912 /* TPDMA: Handles TP-initiated uncached memory accesses:
913 * l[], g[], stack, 2d surfaces, render targets. */
914 if (status & 0x100) {
915 nv50_pgraph_tp_trap(dev, 8, 0x408e08, 0x408708, display,
916 "PGRAPH - TRAP_TPDMA");
917 nv_wr32(dev, 0x400108, 0x100);
918 status &= ~0x100;
919 }
920
921 if (status) {
922 if (display)
923 NV_INFO(dev, "PGRAPH - TRAP: unknown 0x%08x\n", status);
924 nv_wr32(dev, 0x400108, status);
925 }
926
927 return 1;
928}
929
930static int
931nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
932{
933 struct drm_nouveau_private *dev_priv = dev->dev_private;
934 struct nouveau_channel *chan;
935 unsigned long flags;
936 int i;
937
938 spin_lock_irqsave(&dev_priv->channels.lock, flags);
939 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
940 chan = dev_priv->channels.ptr[i];
941 if (!chan || !chan->ramin)
942 continue;
943
944 if (inst == chan->ramin->vinst)
945 break;
946 }
947 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
948 return i;
949}
950
951static void
952nv50_graph_isr(struct drm_device *dev)
953{
954 u32 stat;
955
956 while ((stat = nv_rd32(dev, 0x400100))) {
957 u64 inst = (u64)(nv_rd32(dev, 0x40032c) & 0x0fffffff) << 12;
958 u32 chid = nv50_graph_isr_chid(dev, inst);
959 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
960 u32 subc = (addr & 0x00070000) >> 16;
961 u32 mthd = (addr & 0x00001ffc);
962 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
963 u32 class = nv_rd32(dev, 0x400814);
964 u32 show = stat;
965
966 if (stat & 0x00000010) {
967 if (!nouveau_gpuobj_mthd_call2(dev, chid, class,
968 mthd, data))
969 show &= ~0x00000010;
970 }
971
972 if (stat & 0x00001000) {
973 nv_wr32(dev, 0x400500, 0x00000000);
974 nv_wr32(dev, 0x400100, 0x00001000);
975 nv_mask(dev, 0x40013c, 0x00001000, 0x00000000);
976 nv50_graph_context_switch(dev);
977 stat &= ~0x00001000;
978 show &= ~0x00001000;
979 }
980
981 show = (show && nouveau_ratelimit()) ? show : 0;
982
983 if (show & 0x00100000) {
984 u32 ecode = nv_rd32(dev, 0x400110);
985 NV_INFO(dev, "PGRAPH - DATA_ERROR ");
986 nouveau_enum_print(nv50_data_error_names, ecode);
987 printk("\n");
988 }
989
990 if (stat & 0x00200000) {
991 if (!nv50_pgraph_trap_handler(dev, show, inst, chid))
992 show &= ~0x00200000;
993 }
994
995 nv_wr32(dev, 0x400100, stat);
996 nv_wr32(dev, 0x400500, 0x00010001);
997
998 if (show) {
999 NV_INFO(dev, "PGRAPH -");
1000 nouveau_bitfield_print(nv50_graph_intr, show);
1001 printk("\n");
1002 NV_INFO(dev, "PGRAPH - ch %d (0x%010llx) subc %d "
1003 "class 0x%04x mthd 0x%04x data 0x%08x\n",
1004 chid, inst, subc, class, mthd, data);
1005 }
1006 }
1007
1008 if (nv_rd32(dev, 0x400824) & (1 << 31))
1009 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1010}
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 08:20:35 -0400