diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2011-03-28 19:28:24 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2011-05-15 20:47:37 -0400 |
commit | 7795bee0c437aff7fb188afe750fe79a7a971a2c (patch) | |
tree | 6f875df0805c5e498a0ba407bd6c6b20139bb452 /drivers/gpu/drm/nouveau/nvc0_fifo.c | |
parent | e2966632ae37abdb03a09bc941ee6d7556cd3624 (diff) |
drm/nvc0: decode gpc/hubclient on vm fault
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvc0_fifo.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nvc0_fifo.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c index e6cb17a7fb3e..55a4245c1a67 100644 --- a/drivers/gpu/drm/nouveau/nvc0_fifo.c +++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c | |||
@@ -383,6 +383,32 @@ struct nouveau_enum nvc0_fifo_fault_reason[] = { | |||
383 | {} | 383 | {} |
384 | }; | 384 | }; |
385 | 385 | ||
386 | struct nouveau_enum nvc0_fifo_fault_hubclient[] = { | ||
387 | { 0x01, "PCOPY0" }, | ||
388 | { 0x02, "PCOPY1" }, | ||
389 | { 0x04, "DISPATCH" }, | ||
390 | { 0x05, "CTXCTL" }, | ||
391 | { 0x06, "PFIFO" }, | ||
392 | { 0x07, "BAR_READ" }, | ||
393 | { 0x08, "BAR_WRITE" }, | ||
394 | { 0x0b, "PVP" }, | ||
395 | { 0x0c, "PPPP" }, | ||
396 | { 0x0d, "PBSP" }, | ||
397 | { 0x11, "PCOUNTER" }, | ||
398 | { 0x12, "PDAEMON" }, | ||
399 | { 0x14, "CCACHE" }, | ||
400 | { 0x15, "CCACHE_POST" }, | ||
401 | {} | ||
402 | }; | ||
403 | |||
404 | struct nouveau_enum nvc0_fifo_fault_gpcclient[] = { | ||
405 | { 0x01, "TEX" }, | ||
406 | { 0x0c, "ESETUP" }, | ||
407 | { 0x0e, "CTXCTL" }, | ||
408 | { 0x0f, "PROP" }, | ||
409 | {} | ||
410 | }; | ||
411 | |||
386 | struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = { | 412 | struct nouveau_bitfield nvc0_fifo_subfifo_intr[] = { |
387 | /* { 0x00008000, "" } seen with null ib push */ | 413 | /* { 0x00008000, "" } seen with null ib push */ |
388 | { 0x00200000, "ILLEGAL_MTHD" }, | 414 | { 0x00200000, "ILLEGAL_MTHD" }, |
@@ -397,12 +423,20 @@ nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit) | |||
397 | u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10)); | 423 | u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10)); |
398 | u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10)); | 424 | u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10)); |
399 | u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10)); | 425 | u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10)); |
426 | u32 client = (stat & 0x00001f00) >> 8; | ||
400 | 427 | ||
401 | NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [", | 428 | NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [", |
402 | (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo); | 429 | (stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo); |
403 | nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f); | 430 | nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f); |
404 | printk("] from "); | 431 | printk("] from "); |
405 | nouveau_enum_print(nvc0_fifo_fault_unit, unit); | 432 | nouveau_enum_print(nvc0_fifo_fault_unit, unit); |
433 | if (stat & 0x00000040) { | ||
434 | printk("/"); | ||
435 | nouveau_enum_print(nvc0_fifo_fault_hubclient, client); | ||
436 | } else { | ||
437 | printk("/GPC%d/", (stat & 0x1f000000) >> 24); | ||
438 | nouveau_enum_print(nvc0_fifo_fault_gpcclient, client); | ||
439 | } | ||
406 | printk(" on channel 0x%010llx\n", (u64)inst << 12); | 440 | printk(" on channel 0x%010llx\n", (u64)inst << 12); |
407 | } | 441 | } |
408 | 442 | ||