diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-07-18 20:51:42 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-10-02 23:12:54 -0400 |
commit | e193b1d42c390bf1bff7fa02a5a1202b98e75601 (patch) | |
tree | c31143ea95c00e8b49c12571b10a1b9a200bd490 /drivers/gpu/drm/nouveau/nv84_fence.c | |
parent | 66f247234d1c47da480f687b8104d8935d05b404 (diff) |
drm/nouveau/fence: un-port from nouveau_exec_engine interfaces
Still the same code, but not an "engine" anymore. The fence code is more of
a policy decision rather than exposing mechanisms, so it's not appropriate
to port it to the new engine subsystem.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv84_fence.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv84_fence.c | 48 |
1 files changed, 18 insertions, 30 deletions
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index 721716aacbe0..a1812cab19dc 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c | |||
@@ -78,28 +78,30 @@ nv84_fence_sync(struct nouveau_fence *fence, | |||
78 | static u32 | 78 | static u32 |
79 | nv84_fence_read(struct nouveau_channel *chan) | 79 | nv84_fence_read(struct nouveau_channel *chan) |
80 | { | 80 | { |
81 | struct nv84_fence_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_FENCE); | 81 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
82 | struct nv84_fence_priv *priv = dev_priv->fence.func; | ||
82 | return nv_ro32(priv->mem, chan->id * 16); | 83 | return nv_ro32(priv->mem, chan->id * 16); |
83 | } | 84 | } |
84 | 85 | ||
85 | static void | 86 | static void |
86 | nv84_fence_context_del(struct nouveau_channel *chan, int engine) | 87 | nv84_fence_context_del(struct nouveau_channel *chan) |
87 | { | 88 | { |
88 | struct nv84_fence_chan *fctx = chan->engctx[engine]; | 89 | struct nv84_fence_chan *fctx = chan->fence; |
89 | nouveau_fence_context_del(&fctx->base); | 90 | nouveau_fence_context_del(&fctx->base); |
90 | chan->engctx[engine] = NULL; | 91 | chan->fence = NULL; |
91 | kfree(fctx); | 92 | kfree(fctx); |
92 | } | 93 | } |
93 | 94 | ||
94 | static int | 95 | static int |
95 | nv84_fence_context_new(struct nouveau_channel *chan, int engine) | 96 | nv84_fence_context_new(struct nouveau_channel *chan) |
96 | { | 97 | { |
97 | struct nv84_fence_priv *priv = nv_engine(chan->dev, engine); | 98 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
99 | struct nv84_fence_priv *priv = dev_priv->fence.func; | ||
98 | struct nv84_fence_chan *fctx; | 100 | struct nv84_fence_chan *fctx; |
99 | struct nouveau_gpuobj *obj; | 101 | struct nouveau_gpuobj *obj; |
100 | int ret; | 102 | int ret; |
101 | 103 | ||
102 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); | 104 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); |
103 | if (!fctx) | 105 | if (!fctx) |
104 | return -ENOMEM; | 106 | return -ENOMEM; |
105 | 107 | ||
@@ -116,30 +118,18 @@ nv84_fence_context_new(struct nouveau_channel *chan, int engine) | |||
116 | } | 118 | } |
117 | 119 | ||
118 | if (ret) | 120 | if (ret) |
119 | nv84_fence_context_del(chan, engine); | 121 | nv84_fence_context_del(chan); |
120 | return ret; | 122 | return ret; |
121 | } | 123 | } |
122 | 124 | ||
123 | static int | ||
124 | nv84_fence_fini(struct drm_device *dev, int engine, bool suspend) | ||
125 | { | ||
126 | return 0; | ||
127 | } | ||
128 | |||
129 | static int | ||
130 | nv84_fence_init(struct drm_device *dev, int engine) | ||
131 | { | ||
132 | return 0; | ||
133 | } | ||
134 | |||
135 | static void | 125 | static void |
136 | nv84_fence_destroy(struct drm_device *dev, int engine) | 126 | nv84_fence_destroy(struct drm_device *dev) |
137 | { | 127 | { |
138 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 128 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
139 | struct nv84_fence_priv *priv = nv_engine(dev, engine); | 129 | struct nv84_fence_priv *priv = dev_priv->fence.func; |
140 | 130 | ||
141 | nouveau_gpuobj_ref(NULL, &priv->mem); | 131 | nouveau_gpuobj_ref(NULL, &priv->mem); |
142 | dev_priv->eng[engine] = NULL; | 132 | dev_priv->fence.func = NULL; |
143 | kfree(priv); | 133 | kfree(priv); |
144 | } | 134 | } |
145 | 135 | ||
@@ -155,15 +145,13 @@ nv84_fence_create(struct drm_device *dev) | |||
155 | if (!priv) | 145 | if (!priv) |
156 | return -ENOMEM; | 146 | return -ENOMEM; |
157 | 147 | ||
158 | priv->base.engine.destroy = nv84_fence_destroy; | 148 | priv->base.dtor = nv84_fence_destroy; |
159 | priv->base.engine.init = nv84_fence_init; | 149 | priv->base.context_new = nv84_fence_context_new; |
160 | priv->base.engine.fini = nv84_fence_fini; | 150 | priv->base.context_del = nv84_fence_context_del; |
161 | priv->base.engine.context_new = nv84_fence_context_new; | ||
162 | priv->base.engine.context_del = nv84_fence_context_del; | ||
163 | priv->base.emit = nv84_fence_emit; | 151 | priv->base.emit = nv84_fence_emit; |
164 | priv->base.sync = nv84_fence_sync; | 152 | priv->base.sync = nv84_fence_sync; |
165 | priv->base.read = nv84_fence_read; | 153 | priv->base.read = nv84_fence_read; |
166 | dev_priv->eng[NVOBJ_ENGINE_FENCE] = &priv->base.engine; | 154 | dev_priv->fence.func = priv; |
167 | 155 | ||
168 | ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels, | 156 | ret = nouveau_gpuobj_new(dev, NULL, 16 * pfifo->channels, |
169 | 0x1000, 0, &priv->mem); | 157 | 0x1000, 0, &priv->mem); |
@@ -172,6 +160,6 @@ nv84_fence_create(struct drm_device *dev) | |||
172 | 160 | ||
173 | out: | 161 | out: |
174 | if (ret) | 162 | if (ret) |
175 | nv84_fence_destroy(dev, NVOBJ_ENGINE_FENCE); | 163 | nv84_fence_destroy(dev); |
176 | return ret; | 164 | return ret; |
177 | } | 165 | } |