diff options
author | Alexandre Courbot <acourbot@nvidia.com> | 2015-02-20 04:22:59 -0500 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2015-04-14 03:00:42 -0400 |
commit | eaecf0326f096faaba462eae48a3b30bcb1f7009 (patch) | |
tree | da4d31cc0d0a867786e2cca541d6a89a1541c921 /drivers/gpu/drm/nouveau/nv84_fence.c | |
parent | c6a7b026a3a80662d8f7bb6b4f7821329aa7111b (diff) |
make RAM device optional
Having a RAM device does not make sense for chips like GK20A which have
no dedicated video memory. The dummy RAM device that we used so far
works as a temporary band-aid, but in the longer term it is desirable
for the driver to be able to work without any kind of VRAM.
This patch adds a few conditionals in places where a RAM device was
assumed to be present and allows some more objects to be allocated from
the TT domain, allowing Nouveau to handle GPUs for which
pfb->ram == NULL.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv84_fence.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv84_fence.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c index bf429cabbaa8..a03db4368696 100644 --- a/drivers/gpu/drm/nouveau/nv84_fence.c +++ b/drivers/gpu/drm/nouveau/nv84_fence.c | |||
@@ -215,6 +215,7 @@ nv84_fence_create(struct nouveau_drm *drm) | |||
215 | { | 215 | { |
216 | struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); | 216 | struct nvkm_fifo *pfifo = nvxx_fifo(&drm->device); |
217 | struct nv84_fence_priv *priv; | 217 | struct nv84_fence_priv *priv; |
218 | u32 domain; | ||
218 | int ret; | 219 | int ret; |
219 | 220 | ||
220 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); | 221 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
@@ -231,10 +232,17 @@ nv84_fence_create(struct nouveau_drm *drm) | |||
231 | priv->base.context_base = fence_context_alloc(priv->base.contexts); | 232 | priv->base.context_base = fence_context_alloc(priv->base.contexts); |
232 | priv->base.uevent = true; | 233 | priv->base.uevent = true; |
233 | 234 | ||
234 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, | 235 | /* Use VRAM if there is any ; otherwise fallback to system memory */ |
235 | TTM_PL_FLAG_VRAM, 0, 0, NULL, NULL, &priv->bo); | 236 | domain = drm->device.info.ram_size != 0 ? TTM_PL_FLAG_VRAM : |
237 | /* | ||
238 | * fences created in sysmem must be non-cached or we | ||
239 | * will lose CPU/GPU coherency! | ||
240 | */ | ||
241 | TTM_PL_FLAG_TT | TTM_PL_FLAG_UNCACHED; | ||
242 | ret = nouveau_bo_new(drm->dev, 16 * priv->base.contexts, 0, domain, 0, | ||
243 | 0, NULL, NULL, &priv->bo); | ||
236 | if (ret == 0) { | 244 | if (ret == 0) { |
237 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); | 245 | ret = nouveau_bo_pin(priv->bo, domain, false); |
238 | if (ret == 0) { | 246 | if (ret == 0) { |
239 | ret = nouveau_bo_map(priv->bo); | 247 | ret = nouveau_bo_map(priv->bo); |
240 | if (ret) | 248 | if (ret) |