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authorBen Skeggs <bskeggs@redhat.com>2010-09-01 01:24:31 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-09-24 02:20:14 -0400
commita8eaebc6c52bb0cd243b4cb421068f42d378be9c (patch)
tree12f796e5210d51f78b9fc6ddd4750cf1421373c2 /drivers/gpu/drm/nouveau/nv50_instmem.c
parentde3a6c0a3b642c0c350414d63298a1b19a009290 (diff)
drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanity
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_instmem.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_instmem.c126
1 files changed, 57 insertions, 69 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index 821806c835ba..0af0baf4f1a9 100644
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -32,9 +32,9 @@
32struct nv50_instmem_priv { 32struct nv50_instmem_priv {
33 uint32_t save1700[5]; /* 0x1700->0x1710 */ 33 uint32_t save1700[5]; /* 0x1700->0x1710 */
34 34
35 struct nouveau_gpuobj_ref *pramin_pt; 35 struct nouveau_gpuobj *pramin_pt;
36 struct nouveau_gpuobj_ref *pramin_bar; 36 struct nouveau_gpuobj *pramin_bar;
37 struct nouveau_gpuobj_ref *fb_bar; 37 struct nouveau_gpuobj *fb_bar;
38}; 38};
39 39
40#define NV50_INSTMEM_PAGE_SHIFT 12 40#define NV50_INSTMEM_PAGE_SHIFT 12
@@ -44,15 +44,8 @@ struct nv50_instmem_priv {
44/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN 44/*NOTE: - Assumes 0x1700 already covers the correct MiB of PRAMIN
45 */ 45 */
46#define BAR0_WI32(g, o, v) do { \ 46#define BAR0_WI32(g, o, v) do { \
47 uint32_t offset; \ 47 u32 offset = (g)->vinst + (o); \
48 if ((g)->im_backing) { \ 48 nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v)); \
49 offset = (g)->im_backing_start; \
50 } else { \
51 offset = chan->ramin->gpuobj->im_backing_start; \
52 offset += (g)->im_pramin->start; \
53 } \
54 offset += (o); \
55 nv_wr32(dev, NV_RAMIN + (offset & 0xfffff), (v)); \
56} while (0) 49} while (0)
57 50
58int 51int
@@ -142,8 +135,7 @@ nv50_instmem_init(struct drm_device *dev)
142 INIT_LIST_HEAD(&chan->ramht_refs); 135 INIT_LIST_HEAD(&chan->ramht_refs);
143 136
144 /* Channel's PRAMIN object + heap */ 137 /* Channel's PRAMIN object + heap */
145 ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, 138 ret = nouveau_gpuobj_new_fake(dev, 0, c_offset, c_size, 0, &chan->ramin);
146 NULL, &chan->ramin);
147 if (ret) 139 if (ret)
148 return ret; 140 return ret;
149 141
@@ -152,16 +144,16 @@ nv50_instmem_init(struct drm_device *dev)
152 144
153 /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */ 145 /* RAMFC + zero channel's PRAMIN up to start of VM pagedir */
154 ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc, 146 ret = nouveau_gpuobj_new_fake(dev, c_ramfc, c_offset + c_ramfc,
155 0x4000, 0, NULL, &chan->ramfc); 147 0x4000, 0, &chan->ramfc);
156 if (ret) 148 if (ret)
157 return ret; 149 return ret;
158 150
159 for (i = 0; i < c_vmpd; i += 4) 151 for (i = 0; i < c_vmpd; i += 4)
160 BAR0_WI32(chan->ramin->gpuobj, i, 0); 152 BAR0_WI32(chan->ramin, i, 0);
161 153
162 /* VM page directory */ 154 /* VM page directory */
163 ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd, 155 ret = nouveau_gpuobj_new_fake(dev, c_vmpd, c_offset + c_vmpd,
164 0x4000, 0, &chan->vm_pd, NULL); 156 0x4000, 0, &chan->vm_pd);
165 if (ret) 157 if (ret)
166 return ret; 158 return ret;
167 for (i = 0; i < 0x4000; i += 8) { 159 for (i = 0; i < 0x4000; i += 8) {
@@ -172,8 +164,8 @@ nv50_instmem_init(struct drm_device *dev)
172 /* PRAMIN page table, cheat and map into VM at 0x0000000000. 164 /* PRAMIN page table, cheat and map into VM at 0x0000000000.
173 * We map the entire fake channel into the start of the PRAMIN BAR 165 * We map the entire fake channel into the start of the PRAMIN BAR
174 */ 166 */
175 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pt_size, 0x1000, 167 ret = nouveau_gpuobj_new(dev, chan, pt_size, 0x1000, 0,
176 0, &priv->pramin_pt); 168 &priv->pramin_pt);
177 if (ret) 169 if (ret)
178 return ret; 170 return ret;
179 171
@@ -185,76 +177,74 @@ nv50_instmem_init(struct drm_device *dev)
185 177
186 i = 0; 178 i = 0;
187 while (v < dev_priv->vram_sys_base + c_offset + c_size) { 179 while (v < dev_priv->vram_sys_base + c_offset + c_size) {
188 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, lower_32_bits(v)); 180 BAR0_WI32(priv->pramin_pt, i + 0, lower_32_bits(v));
189 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, upper_32_bits(v)); 181 BAR0_WI32(priv->pramin_pt, i + 4, upper_32_bits(v));
190 v += 0x1000; 182 v += 0x1000;
191 i += 8; 183 i += 8;
192 } 184 }
193 185
194 while (i < pt_size) { 186 while (i < pt_size) {
195 BAR0_WI32(priv->pramin_pt->gpuobj, i + 0, 0x00000000); 187 BAR0_WI32(priv->pramin_pt, i + 0, 0x00000000);
196 BAR0_WI32(priv->pramin_pt->gpuobj, i + 4, 0x00000000); 188 BAR0_WI32(priv->pramin_pt, i + 4, 0x00000000);
197 i += 8; 189 i += 8;
198 } 190 }
199 191
200 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->instance | 0x63); 192 BAR0_WI32(chan->vm_pd, 0x00, priv->pramin_pt->vinst | 0x63);
201 BAR0_WI32(chan->vm_pd, 0x04, 0x00000000); 193 BAR0_WI32(chan->vm_pd, 0x04, 0x00000000);
202 194
203 /* VRAM page table(s), mapped into VM at +1GiB */ 195 /* VRAM page table(s), mapped into VM at +1GiB */
204 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { 196 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) {
205 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, 197 ret = nouveau_gpuobj_new(dev, chan, NV50_VM_BLOCK / 0x10000 * 8,
206 NV50_VM_BLOCK/65536*8, 0, 0, 198 0, 0, &chan->vm_vram_pt[i]);
207 &chan->vm_vram_pt[i]);
208 if (ret) { 199 if (ret) {
209 NV_ERROR(dev, "Error creating VRAM page tables: %d\n", 200 NV_ERROR(dev, "Error creating VRAM page tables: %d\n",
210 ret); 201 ret);
211 dev_priv->vm_vram_pt_nr = i; 202 dev_priv->vm_vram_pt_nr = i;
212 return ret; 203 return ret;
213 } 204 }
214 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i]->gpuobj; 205 /*XXX: double-check this is ok */
206 dev_priv->vm_vram_pt[i] = chan->vm_vram_pt[i];
215 207
216 for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size; 208 for (v = 0; v < dev_priv->vm_vram_pt[i]->im_pramin->size;
217 v += 4) 209 v += 4)
218 BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0); 210 BAR0_WI32(dev_priv->vm_vram_pt[i], v, 0);
219 211
220 BAR0_WI32(chan->vm_pd, 0x10 + (i*8), 212 BAR0_WI32(chan->vm_pd, 0x10 + (i*8),
221 chan->vm_vram_pt[i]->instance | 0x61); 213 chan->vm_vram_pt[i]->vinst | 0x61);
222 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0); 214 BAR0_WI32(chan->vm_pd, 0x14 + (i*8), 0);
223 } 215 }
224 216
225 /* DMA object for PRAMIN BAR */ 217 /* DMA object for PRAMIN BAR */
226 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0, 218 ret = nouveau_gpuobj_new(dev, chan, 6*4, 16, 0, &priv->pramin_bar);
227 &priv->pramin_bar);
228 if (ret) 219 if (ret)
229 return ret; 220 return ret;
230 BAR0_WI32(priv->pramin_bar->gpuobj, 0x00, 0x7fc00000); 221 BAR0_WI32(priv->pramin_bar, 0x00, 0x7fc00000);
231 BAR0_WI32(priv->pramin_bar->gpuobj, 0x04, dev_priv->ramin_size - 1); 222 BAR0_WI32(priv->pramin_bar, 0x04, dev_priv->ramin_size - 1);
232 BAR0_WI32(priv->pramin_bar->gpuobj, 0x08, 0x00000000); 223 BAR0_WI32(priv->pramin_bar, 0x08, 0x00000000);
233 BAR0_WI32(priv->pramin_bar->gpuobj, 0x0c, 0x00000000); 224 BAR0_WI32(priv->pramin_bar, 0x0c, 0x00000000);
234 BAR0_WI32(priv->pramin_bar->gpuobj, 0x10, 0x00000000); 225 BAR0_WI32(priv->pramin_bar, 0x10, 0x00000000);
235 BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000); 226 BAR0_WI32(priv->pramin_bar, 0x14, 0x00000000);
236 227
237 /* DMA object for FB BAR */ 228 /* DMA object for FB BAR */
238 ret = nouveau_gpuobj_new_ref(dev, chan, chan, 0, 6*4, 16, 0, 229 ret = nouveau_gpuobj_new(dev, chan, 6*4, 16, 0, &priv->fb_bar);
239 &priv->fb_bar);
240 if (ret) 230 if (ret)
241 return ret; 231 return ret;
242 BAR0_WI32(priv->fb_bar->gpuobj, 0x00, 0x7fc00000); 232 BAR0_WI32(priv->fb_bar, 0x00, 0x7fc00000);
243 BAR0_WI32(priv->fb_bar->gpuobj, 0x04, 0x40000000 + 233 BAR0_WI32(priv->fb_bar, 0x04, 0x40000000 +
244 pci_resource_len(dev->pdev, 1) - 1); 234 pci_resource_len(dev->pdev, 1) - 1);
245 BAR0_WI32(priv->fb_bar->gpuobj, 0x08, 0x40000000); 235 BAR0_WI32(priv->fb_bar, 0x08, 0x40000000);
246 BAR0_WI32(priv->fb_bar->gpuobj, 0x0c, 0x00000000); 236 BAR0_WI32(priv->fb_bar, 0x0c, 0x00000000);
247 BAR0_WI32(priv->fb_bar->gpuobj, 0x10, 0x00000000); 237 BAR0_WI32(priv->fb_bar, 0x10, 0x00000000);
248 BAR0_WI32(priv->fb_bar->gpuobj, 0x14, 0x00000000); 238 BAR0_WI32(priv->fb_bar, 0x14, 0x00000000);
249 239
250 /* Poke the relevant regs, and pray it works :) */ 240 /* Poke the relevant regs, and pray it works :) */
251 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12)); 241 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
252 nv_wr32(dev, NV50_PUNK_UNK1710, 0); 242 nv_wr32(dev, NV50_PUNK_UNK1710, 0);
253 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) | 243 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
254 NV50_PUNK_BAR_CFG_BASE_VALID); 244 NV50_PUNK_BAR_CFG_BASE_VALID);
255 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) | 245 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->cinst >> 4) |
256 NV50_PUNK_BAR1_CTXDMA_VALID); 246 NV50_PUNK_BAR1_CTXDMA_VALID);
257 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) | 247 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->cinst >> 4) |
258 NV50_PUNK_BAR3_CTXDMA_VALID); 248 NV50_PUNK_BAR3_CTXDMA_VALID);
259 249
260 for (i = 0; i < 8; i++) 250 for (i = 0; i < 8; i++)
@@ -301,21 +291,19 @@ nv50_instmem_takedown(struct drm_device *dev)
301 for (i = 0x1700; i <= 0x1710; i += 4) 291 for (i = 0x1700; i <= 0x1710; i += 4)
302 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]); 292 nv_wr32(dev, i, priv->save1700[(i - 0x1700) / 4]);
303 293
304 nouveau_gpuobj_ref_del(dev, &priv->fb_bar); 294 nouveau_gpuobj_ref(NULL, &priv->fb_bar);
305 nouveau_gpuobj_ref_del(dev, &priv->pramin_bar); 295 nouveau_gpuobj_ref(NULL, &priv->pramin_bar);
306 nouveau_gpuobj_ref_del(dev, &priv->pramin_pt); 296 nouveau_gpuobj_ref(NULL, &priv->pramin_pt);
307 297
308 /* Destroy dummy channel */ 298 /* Destroy dummy channel */
309 if (chan) { 299 if (chan) {
310 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { 300 for (i = 0; i < dev_priv->vm_vram_pt_nr; i++)
311 nouveau_gpuobj_ref_del(dev, &chan->vm_vram_pt[i]); 301 nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]);
312 dev_priv->vm_vram_pt[i] = NULL;
313 }
314 dev_priv->vm_vram_pt_nr = 0; 302 dev_priv->vm_vram_pt_nr = 0;
315 303
316 nouveau_gpuobj_del(dev, &chan->vm_pd); 304 nouveau_gpuobj_ref(NULL, &chan->vm_pd);
317 nouveau_gpuobj_ref_del(dev, &chan->ramfc); 305 nouveau_gpuobj_ref(NULL, &chan->ramfc);
318 nouveau_gpuobj_ref_del(dev, &chan->ramin); 306 nouveau_gpuobj_ref(NULL, &chan->ramin);
319 drm_mm_takedown(&chan->ramin_heap); 307 drm_mm_takedown(&chan->ramin_heap);
320 308
321 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL; 309 dev_priv->fifos[0] = dev_priv->fifos[127] = NULL;
@@ -331,7 +319,7 @@ nv50_instmem_suspend(struct drm_device *dev)
331{ 319{
332 struct drm_nouveau_private *dev_priv = dev->dev_private; 320 struct drm_nouveau_private *dev_priv = dev->dev_private;
333 struct nouveau_channel *chan = dev_priv->fifos[0]; 321 struct nouveau_channel *chan = dev_priv->fifos[0];
334 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; 322 struct nouveau_gpuobj *ramin = chan->ramin;
335 int i; 323 int i;
336 324
337 ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size); 325 ramin->im_backing_suspend = vmalloc(ramin->im_pramin->size);
@@ -349,7 +337,7 @@ nv50_instmem_resume(struct drm_device *dev)
349 struct drm_nouveau_private *dev_priv = dev->dev_private; 337 struct drm_nouveau_private *dev_priv = dev->dev_private;
350 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv; 338 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
351 struct nouveau_channel *chan = dev_priv->fifos[0]; 339 struct nouveau_channel *chan = dev_priv->fifos[0];
352 struct nouveau_gpuobj *ramin = chan->ramin->gpuobj; 340 struct nouveau_gpuobj *ramin = chan->ramin;
353 int i; 341 int i;
354 342
355 nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16)); 343 nv_wr32(dev, NV50_PUNK_BAR0_PRAMIN, (ramin->im_backing_start >> 16));
@@ -359,13 +347,13 @@ nv50_instmem_resume(struct drm_device *dev)
359 ramin->im_backing_suspend = NULL; 347 ramin->im_backing_suspend = NULL;
360 348
361 /* Poke the relevant regs, and pray it works :) */ 349 /* Poke the relevant regs, and pray it works :) */
362 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12)); 350 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12));
363 nv_wr32(dev, NV50_PUNK_UNK1710, 0); 351 nv_wr32(dev, NV50_PUNK_UNK1710, 0);
364 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) | 352 nv_wr32(dev, NV50_PUNK_BAR_CFG_BASE, (chan->ramin->vinst >> 12) |
365 NV50_PUNK_BAR_CFG_BASE_VALID); 353 NV50_PUNK_BAR_CFG_BASE_VALID);
366 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->instance >> 4) | 354 nv_wr32(dev, NV50_PUNK_BAR1_CTXDMA, (priv->fb_bar->cinst >> 4) |
367 NV50_PUNK_BAR1_CTXDMA_VALID); 355 NV50_PUNK_BAR1_CTXDMA_VALID);
368 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) | 356 nv_wr32(dev, NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->cinst >> 4) |
369 NV50_PUNK_BAR3_CTXDMA_VALID); 357 NV50_PUNK_BAR3_CTXDMA_VALID);
370 358
371 for (i = 0; i < 8; i++) 359 for (i = 0; i < 8; i++)
@@ -424,7 +412,7 @@ nv50_instmem_bind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
424{ 412{
425 struct drm_nouveau_private *dev_priv = dev->dev_private; 413 struct drm_nouveau_private *dev_priv = dev->dev_private;
426 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv; 414 struct nv50_instmem_priv *priv = dev_priv->engine.instmem.priv;
427 struct nouveau_gpuobj *pramin_pt = priv->pramin_pt->gpuobj; 415 struct nouveau_gpuobj *pramin_pt = priv->pramin_pt;
428 uint32_t pte, pte_end; 416 uint32_t pte, pte_end;
429 uint64_t vram; 417 uint64_t vram;
430 418
@@ -477,8 +465,8 @@ nv50_instmem_unbind(struct drm_device *dev, struct nouveau_gpuobj *gpuobj)
477 pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte; 465 pte_end = ((gpuobj->im_pramin->size >> 12) << 1) + pte;
478 466
479 while (pte < pte_end) { 467 while (pte < pte_end) {
480 nv_wo32(priv->pramin_pt->gpuobj, (pte * 4) + 0, 0x00000000); 468 nv_wo32(priv->pramin_pt, (pte * 4) + 0, 0x00000000);
481 nv_wo32(priv->pramin_pt->gpuobj, (pte * 4) + 4, 0x00000000); 469 nv_wo32(priv->pramin_pt, (pte * 4) + 4, 0x00000000);
482 pte += 2; 470 pte += 2;
483 } 471 }
484 dev_priv->engine.instmem.flush(dev); 472 dev_priv->engine.instmem.flush(dev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-23 18:20:49 -0400