diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-07-07 21:29:10 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-07-12 20:13:40 -0400 |
commit | f56cb86f9abd229418f894a8ffedfb9ff465c181 (patch) | |
tree | b29420af53d096e49ff573790c6161ed71599858 /drivers/gpu/drm/nouveau/nv50_graph.c | |
parent | 2107cce3056dccf37ae5cbfc95df348959b2c717 (diff) |
drm/nouveau: add instmem flush() hook
This removes the previous prepare_access() and finish_access() hooks, and
replaces it with a much simpler flush() hook.
All the chipset-specific code before nv50 has its use removed completely,
as it's not required there at all.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_graph.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_graph.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c index b04e7c8449a5..5dc3be5696a9 100644 --- a/drivers/gpu/drm/nouveau/nv50_graph.c +++ b/drivers/gpu/drm/nouveau/nv50_graph.c | |||
@@ -226,7 +226,6 @@ nv50_graph_create_context(struct nouveau_channel *chan) | |||
226 | obj = chan->ramin_grctx->gpuobj; | 226 | obj = chan->ramin_grctx->gpuobj; |
227 | 227 | ||
228 | hdr = IS_G80 ? 0x200 : 0x20; | 228 | hdr = IS_G80 ? 0x200 : 0x20; |
229 | dev_priv->engine.instmem.prepare_access(dev, true); | ||
230 | nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002); | 229 | nv_wo32(dev, ramin, (hdr + 0x00)/4, 0x00190002); |
231 | nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + | 230 | nv_wo32(dev, ramin, (hdr + 0x04)/4, chan->ramin_grctx->instance + |
232 | pgraph->grctx_size - 1); | 231 | pgraph->grctx_size - 1); |
@@ -234,9 +233,7 @@ nv50_graph_create_context(struct nouveau_channel *chan) | |||
234 | nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0); | 233 | nv_wo32(dev, ramin, (hdr + 0x0c)/4, 0); |
235 | nv_wo32(dev, ramin, (hdr + 0x10)/4, 0); | 234 | nv_wo32(dev, ramin, (hdr + 0x10)/4, 0); |
236 | nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000); | 235 | nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000); |
237 | dev_priv->engine.instmem.finish_access(dev); | ||
238 | 236 | ||
239 | dev_priv->engine.instmem.prepare_access(dev, true); | ||
240 | if (!pgraph->ctxprog) { | 237 | if (!pgraph->ctxprog) { |
241 | struct nouveau_grctx ctx = {}; | 238 | struct nouveau_grctx ctx = {}; |
242 | ctx.dev = chan->dev; | 239 | ctx.dev = chan->dev; |
@@ -247,8 +244,8 @@ nv50_graph_create_context(struct nouveau_channel *chan) | |||
247 | nouveau_grctx_vals_load(dev, obj); | 244 | nouveau_grctx_vals_load(dev, obj); |
248 | } | 245 | } |
249 | nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12); | 246 | nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12); |
250 | dev_priv->engine.instmem.finish_access(dev); | ||
251 | 247 | ||
248 | dev_priv->engine.instmem.flush(dev); | ||
252 | return 0; | 249 | return 0; |
253 | } | 250 | } |
254 | 251 | ||
@@ -264,10 +261,9 @@ nv50_graph_destroy_context(struct nouveau_channel *chan) | |||
264 | if (!chan->ramin || !chan->ramin->gpuobj) | 261 | if (!chan->ramin || !chan->ramin->gpuobj) |
265 | return; | 262 | return; |
266 | 263 | ||
267 | dev_priv->engine.instmem.prepare_access(dev, true); | ||
268 | for (i = hdr; i < hdr + 24; i += 4) | 264 | for (i = hdr; i < hdr + 24; i += 4) |
269 | nv_wo32(dev, chan->ramin->gpuobj, i/4, 0); | 265 | nv_wo32(dev, chan->ramin->gpuobj, i/4, 0); |
270 | dev_priv->engine.instmem.finish_access(dev); | 266 | dev_priv->engine.instmem.flush(dev); |
271 | 267 | ||
272 | nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); | 268 | nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); |
273 | } | 269 | } |