aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/nouveau/nv50_fifo.c
diff options
context:
space:
mode:
authorBen Skeggs <bskeggs@redhat.com>2010-11-22 01:05:54 -0500
committerFrancisco Jerez <currojerez@riseup.net>2010-12-07 21:00:34 -0500
commitd908175cca901b95ba1628428b216e6e7188e8fb (patch)
tree720e95c36101ca4fa2d46792c58bd2456c2df8db /drivers/gpu/drm/nouveau/nv50_fifo.c
parent395a31ec7ed9b02c5412f4405acbd6fceacca0fc (diff)
drm/nouveau: make fifo.create_context() responsible for mapping control regs
The regs belong to PFIFO, they're different for pretty much the same generations we need different PFIFO control for, and NVC0 is going to be even more different than the rest. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_fifo.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c
index ed18952ae7f4..7add3dfde3df 100644
--- a/drivers/gpu/drm/nouveau/nv50_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c
@@ -261,6 +261,11 @@ nv50_fifo_create_context(struct nouveau_channel *chan)
261 } 261 }
262 ramfc = chan->ramfc; 262 ramfc = chan->ramfc;
263 263
264 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
265 NV50_USER(chan->id), PAGE_SIZE);
266 if (!chan->user)
267 return -ENOMEM;
268
264 spin_lock_irqsave(&dev_priv->context_switch_lock, flags); 269 spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
265 270
266 nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4); 271 nv_wo32(ramfc, 0x48, chan->pushbuf->cinst >> 4);
@@ -327,6 +332,10 @@ nv50_fifo_destroy_context(struct nouveau_channel *chan)
327 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 332 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
328 333
329 /* Free the channel resources */ 334 /* Free the channel resources */
335 if (chan->user) {
336 iounmap(chan->user);
337 chan->user = NULL;
338 }
330 nouveau_gpuobj_ref(NULL, &ramfc); 339 nouveau_gpuobj_ref(NULL, &ramfc);
331 nouveau_gpuobj_ref(NULL, &chan->cache); 340 nouveau_gpuobj_ref(NULL, &chan->cache);
332} 341}