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authorBen Skeggs <bskeggs@redhat.com>2011-01-31 19:24:41 -0500
committerBen Skeggs <bskeggs@redhat.com>2011-02-24 15:44:42 -0500
commit59c0f5780f21ef10428bdaccd9999879f38225bc (patch)
tree2076a40142fa4472cb4481ce98c43f0025bc8b9a /drivers/gpu/drm/nouveau/nv50_evo.c
parentef8389a84bbd80daaf6c60a5534461d82ba22c0a (diff)
drm/nv50-nvc0: rename disp->evo to disp->master
More appropriate, and we're about to be using more than just the master EVO channel. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_evo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_evo.c42
1 files changed, 21 insertions, 21 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c
index d3222a73c28e..d837168b5aa5 100644
--- a/drivers/gpu/drm/nouveau/nv50_evo.c
+++ b/drivers/gpu/drm/nouveau/nv50_evo.c
@@ -62,7 +62,7 @@ nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 class, u32 name,
62 struct nouveau_gpuobj *obj = NULL; 62 struct nouveau_gpuobj *obj = NULL;
63 int ret; 63 int ret;
64 64
65 ret = nouveau_gpuobj_new(evo->dev, disp->evo, 6*4, 32, 0, &obj); 65 ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
66 if (ret) 66 if (ret)
67 return ret; 67 return ret;
68 obj->engine = NVOBJ_ENGINE_DISPLAY; 68 obj->engine = NVOBJ_ENGINE_DISPLAY;
@@ -139,8 +139,8 @@ nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pevo)
139 } 139 }
140 140
141 /* bind primary evo channel's ramht to the channel */ 141 /* bind primary evo channel's ramht to the channel */
142 if (disp->evo && evo != disp->evo) 142 if (disp->master && evo != disp->master)
143 nouveau_ramht_ref(disp->evo->ramht, &evo->ramht, NULL); 143 nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
144 144
145 return 0; 145 return 0;
146} 146}
@@ -225,10 +225,10 @@ nv50_evo_create(struct drm_device *dev)
225 /* create primary evo channel, the one we use for modesetting 225 /* create primary evo channel, the one we use for modesetting
226 * purporses 226 * purporses
227 */ 227 */
228 ret = nv50_evo_channel_new(dev, &disp->evo); 228 ret = nv50_evo_channel_new(dev, &disp->master);
229 if (ret) 229 if (ret)
230 return ret; 230 return ret;
231 evo = disp->evo; 231 evo = disp->master;
232 232
233 /* setup object management on it, any other evo channel will 233 /* setup object management on it, any other evo channel will
234 * use this also as there's no per-channel support on the 234 * use this also as there's no per-channel support on the
@@ -238,28 +238,28 @@ nv50_evo_create(struct drm_device *dev)
238 NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin); 238 NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
239 if (ret) { 239 if (ret) {
240 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret); 240 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
241 nv50_evo_channel_del(&disp->evo); 241 nv50_evo_channel_del(&disp->master);
242 return ret; 242 return ret;
243 } 243 }
244 244
245 ret = drm_mm_init(&evo->ramin_heap, 0, 32768); 245 ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
246 if (ret) { 246 if (ret) {
247 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret); 247 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
248 nv50_evo_channel_del(&disp->evo); 248 nv50_evo_channel_del(&disp->master);
249 return ret; 249 return ret;
250 } 250 }
251 251
252 ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht); 252 ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
253 if (ret) { 253 if (ret) {
254 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret); 254 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
255 nv50_evo_channel_del(&disp->evo); 255 nv50_evo_channel_del(&disp->master);
256 return ret; 256 return ret;
257 } 257 }
258 258
259 ret = nouveau_ramht_new(dev, ramht, &evo->ramht); 259 ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
260 nouveau_gpuobj_ref(NULL, &ramht); 260 nouveau_gpuobj_ref(NULL, &ramht);
261 if (ret) { 261 if (ret) {
262 nv50_evo_channel_del(&disp->evo); 262 nv50_evo_channel_del(&disp->master);
263 return ret; 263 return ret;
264 } 264 }
265 265
@@ -268,28 +268,28 @@ nv50_evo_create(struct drm_device *dev)
268 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19, 268 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0xfe, 0x19,
269 0, 0xffffffff, 0x00000000); 269 0, 0xffffffff, 0x00000000);
270 if (ret) { 270 if (ret) {
271 nv50_evo_channel_del(&disp->evo); 271 nv50_evo_channel_del(&disp->master);
272 return ret; 272 return ret;
273 } 273 }
274 274
275 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19, 275 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
276 0, dev_priv->vram_size, 0x00020000); 276 0, dev_priv->vram_size, 0x00020000);
277 if (ret) { 277 if (ret) {
278 nv50_evo_channel_del(&disp->evo); 278 nv50_evo_channel_del(&disp->master);
279 return ret; 279 return ret;
280 } 280 }
281 281
282 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19, 282 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
283 0, dev_priv->vram_size, 0x00000000); 283 0, dev_priv->vram_size, 0x00000000);
284 if (ret) { 284 if (ret) {
285 nv50_evo_channel_del(&disp->evo); 285 nv50_evo_channel_del(&disp->master);
286 return ret; 286 return ret;
287 } 287 }
288 } else { 288 } else {
289 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19, 289 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB16, 0x70, 0x19,
290 0, 0xffffffff, 0x00010000); 290 0, 0xffffffff, 0x00010000);
291 if (ret) { 291 if (ret) {
292 nv50_evo_channel_del(&disp->evo); 292 nv50_evo_channel_del(&disp->master);
293 return ret; 293 return ret;
294 } 294 }
295 295
@@ -297,21 +297,21 @@ nv50_evo_create(struct drm_device *dev)
297 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19, 297 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoFB32, 0x7a, 0x19,
298 0, 0xffffffff, 0x00010000); 298 0, 0xffffffff, 0x00010000);
299 if (ret) { 299 if (ret) {
300 nv50_evo_channel_del(&disp->evo); 300 nv50_evo_channel_del(&disp->master);
301 return ret; 301 return ret;
302 } 302 }
303 303
304 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19, 304 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM, 0, 0x19,
305 0, dev_priv->vram_size, 0x00010000); 305 0, dev_priv->vram_size, 0x00010000);
306 if (ret) { 306 if (ret) {
307 nv50_evo_channel_del(&disp->evo); 307 nv50_evo_channel_del(&disp->master);
308 return ret; 308 return ret;
309 } 309 }
310 310
311 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19, 311 ret = nv50_evo_dmaobj_new(evo, 0x3d, NvEvoVRAM_LP, 0, 0x19,
312 0, dev_priv->vram_size, 0x00010000); 312 0, dev_priv->vram_size, 0x00010000);
313 if (ret) { 313 if (ret) {
314 nv50_evo_channel_del(&disp->evo); 314 nv50_evo_channel_del(&disp->master);
315 return ret; 315 return ret;
316 } 316 }
317 } 317 }
@@ -325,13 +325,13 @@ nv50_evo_init(struct drm_device *dev)
325 struct nv50_display *disp = nv50_display(dev); 325 struct nv50_display *disp = nv50_display(dev);
326 int ret; 326 int ret;
327 327
328 if (!disp->evo) { 328 if (!disp->master) {
329 ret = nv50_evo_create(dev); 329 ret = nv50_evo_create(dev);
330 if (ret) 330 if (ret)
331 return ret; 331 return ret;
332 } 332 }
333 333
334 return nv50_evo_channel_init(disp->evo); 334 return nv50_evo_channel_init(disp->master);
335} 335}
336 336
337void 337void
@@ -339,8 +339,8 @@ nv50_evo_fini(struct drm_device *dev)
339{ 339{
340 struct nv50_display *disp = nv50_display(dev); 340 struct nv50_display *disp = nv50_display(dev);
341 341
342 if (disp->evo) { 342 if (disp->master) {
343 nv50_evo_channel_fini(disp->evo); 343 nv50_evo_channel_fini(disp->master);
344 nv50_evo_channel_del(&disp->evo); 344 nv50_evo_channel_del(&disp->master);
345 } 345 }
346} 346}