diff options
author | Francisco Jerez <currojerez@riseup.net> | 2010-09-07 11:34:44 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-09-24 02:25:36 -0400 |
commit | 4b5c152a79d512803ea525b0878ccef627cd1629 (patch) | |
tree | ea046ac2be1e30a4e08c7ece4b8e1c787aa0ef42 /drivers/gpu/drm/nouveau/nv50_display.c | |
parent | 35fd5b42f035c795bd9c6649591f59b500cb62b3 (diff) |
drm/nouveau: Remove implicit argument from nv_wait().
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv50_display.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c index c11a2fa43c7f..11d366ad4036 100644 --- a/drivers/gpu/drm/nouveau/nv50_display.c +++ b/drivers/gpu/drm/nouveau/nv50_display.c | |||
@@ -279,7 +279,7 @@ nv50_display_init(struct drm_device *dev) | |||
279 | if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { | 279 | if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) { |
280 | nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); | 280 | nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100); |
281 | nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); | 281 | nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1); |
282 | if (!nv_wait(0x006194e8, 2, 0)) { | 282 | if (!nv_wait(dev, 0x006194e8, 2, 0)) { |
283 | NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); | 283 | NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n"); |
284 | NV_ERROR(dev, "0x6194e8 = 0x%08x\n", | 284 | NV_ERROR(dev, "0x6194e8 = 0x%08x\n", |
285 | nv_rd32(dev, 0x6194e8)); | 285 | nv_rd32(dev, 0x6194e8)); |
@@ -310,7 +310,8 @@ nv50_display_init(struct drm_device *dev) | |||
310 | 310 | ||
311 | nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE); | 311 | nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE); |
312 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03); | 312 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03); |
313 | if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x40000000, 0x40000000)) { | 313 | if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), |
314 | 0x40000000, 0x40000000)) { | ||
314 | NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n"); | 315 | NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n"); |
315 | NV_ERROR(dev, "0x610200 = 0x%08x\n", | 316 | NV_ERROR(dev, "0x610200 = 0x%08x\n", |
316 | nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); | 317 | nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); |
@@ -319,7 +320,7 @@ nv50_display_init(struct drm_device *dev) | |||
319 | 320 | ||
320 | for (i = 0; i < 2; i++) { | 321 | for (i = 0; i < 2; i++) { |
321 | nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); | 322 | nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000); |
322 | if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), | 323 | if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), |
323 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { | 324 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) { |
324 | NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); | 325 | NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n"); |
325 | NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", | 326 | NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n", |
@@ -329,7 +330,7 @@ nv50_display_init(struct drm_device *dev) | |||
329 | 330 | ||
330 | nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), | 331 | nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), |
331 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); | 332 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON); |
332 | if (!nv_wait(NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), | 333 | if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), |
333 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, | 334 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, |
334 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { | 335 | NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) { |
335 | NV_ERROR(dev, "timeout: " | 336 | NV_ERROR(dev, "timeout: " |
@@ -349,7 +350,7 @@ nv50_display_init(struct drm_device *dev) | |||
349 | NV50_PDISPLAY_CHANNEL_DMA_CB_VALID); | 350 | NV50_PDISPLAY_CHANNEL_DMA_CB_VALID); |
350 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000); | 351 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000); |
351 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002); | 352 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002); |
352 | if (!nv_wait(0x610200, 0x80000000, 0x00000000)) { | 353 | if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) { |
353 | NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n"); | 354 | NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n"); |
354 | NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200)); | 355 | NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200)); |
355 | return -EBUSY; | 356 | return -EBUSY; |
@@ -389,7 +390,7 @@ nv50_display_init(struct drm_device *dev) | |||
389 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1); | 390 | BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1); |
390 | OUT_RING(evo, 0); | 391 | OUT_RING(evo, 0); |
391 | FIRE_RING(evo); | 392 | FIRE_RING(evo); |
392 | if (!nv_wait(0x640004, 0xffffffff, evo->dma.put << 2)) | 393 | if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2)) |
393 | NV_ERROR(dev, "evo pushbuf stalled\n"); | 394 | NV_ERROR(dev, "evo pushbuf stalled\n"); |
394 | 395 | ||
395 | /* enable clock change interrupts. */ | 396 | /* enable clock change interrupts. */ |
@@ -443,7 +444,7 @@ static int nv50_display_disable(struct drm_device *dev) | |||
443 | continue; | 444 | continue; |
444 | 445 | ||
445 | nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); | 446 | nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask); |
446 | if (!nv_wait(NV50_PDISPLAY_INTR_1, mask, mask)) { | 447 | if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) { |
447 | NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " | 448 | NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == " |
448 | "0x%08x\n", mask, mask); | 449 | "0x%08x\n", mask, mask); |
449 | NV_ERROR(dev, "0x610024 = 0x%08x\n", | 450 | NV_ERROR(dev, "0x610024 = 0x%08x\n", |
@@ -453,14 +454,14 @@ static int nv50_display_disable(struct drm_device *dev) | |||
453 | 454 | ||
454 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0); | 455 | nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0); |
455 | nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0); | 456 | nv_wr32(dev, NV50_PDISPLAY_CTRL_STATE, 0); |
456 | if (!nv_wait(NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) { | 457 | if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) { |
457 | NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n"); | 458 | NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n"); |
458 | NV_ERROR(dev, "0x610200 = 0x%08x\n", | 459 | NV_ERROR(dev, "0x610200 = 0x%08x\n", |
459 | nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); | 460 | nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))); |
460 | } | 461 | } |
461 | 462 | ||
462 | for (i = 0; i < 3; i++) { | 463 | for (i = 0; i < 3; i++) { |
463 | if (!nv_wait(NV50_PDISPLAY_SOR_DPMS_STATE(i), | 464 | if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), |
464 | NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { | 465 | NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) { |
465 | NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); | 466 | NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i); |
466 | NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, | 467 | NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i, |