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authorBen Skeggs <bskeggs@redhat.com>2010-10-18 23:05:51 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-12-03 00:10:52 -0500
commitb7bc613a4cc08d867b43189c2af0bb83b1fa1dc6 (patch)
tree9f82aa99db8499a5f0eca1db4ae1b34352e92584 /drivers/gpu/drm/nouveau/nv50_display.c
parent106ddad5aa8e8e03503cea05f9a64611f849952f (diff)
drm/nv50: move evo handling to nv50_evo.c
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv50_display.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv50_display.c238
1 files changed, 5 insertions, 233 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 7c9c7c5bf22a..db100a8f231e 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -46,159 +46,6 @@ nv50_sor_nr(struct drm_device *dev)
46 return 4; 46 return 4;
47} 47}
48 48
49static void
50nv50_evo_channel_del(struct nouveau_channel **pchan)
51{
52 struct nouveau_channel *chan = *pchan;
53
54 if (!chan)
55 return;
56 *pchan = NULL;
57
58 nouveau_gpuobj_channel_takedown(chan);
59 nouveau_bo_unmap(chan->pushbuf_bo);
60 nouveau_bo_ref(NULL, &chan->pushbuf_bo);
61
62 if (chan->user)
63 iounmap(chan->user);
64
65 kfree(chan);
66}
67
68static int
69nv50_evo_dmaobj_new(struct nouveau_channel *evo, uint32_t class, uint32_t name,
70 uint32_t tile_flags, uint32_t magic_flags,
71 uint32_t offset, uint32_t limit)
72{
73 struct drm_nouveau_private *dev_priv = evo->dev->dev_private;
74 struct drm_device *dev = evo->dev;
75 struct nouveau_gpuobj *obj = NULL;
76 int ret;
77
78 ret = nouveau_gpuobj_new(dev, evo, 6*4, 32, 0, &obj);
79 if (ret)
80 return ret;
81 obj->engine = NVOBJ_ENGINE_DISPLAY;
82
83 nv_wo32(obj, 0, (tile_flags << 22) | (magic_flags << 16) | class);
84 nv_wo32(obj, 4, limit);
85 nv_wo32(obj, 8, offset);
86 nv_wo32(obj, 12, 0x00000000);
87 nv_wo32(obj, 16, 0x00000000);
88 if (dev_priv->card_type < NV_C0)
89 nv_wo32(obj, 20, 0x00010000);
90 else
91 nv_wo32(obj, 20, 0x00020000);
92 dev_priv->engine.instmem.flush(dev);
93
94 ret = nouveau_ramht_insert(evo, name, obj);
95 nouveau_gpuobj_ref(NULL, &obj);
96 if (ret) {
97 return ret;
98 }
99
100 return 0;
101}
102
103static int
104nv50_evo_channel_new(struct drm_device *dev, struct nouveau_channel **pchan)
105{
106 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 struct nouveau_gpuobj *ramht = NULL;
108 struct nouveau_channel *chan;
109 int ret;
110
111 chan = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
112 if (!chan)
113 return -ENOMEM;
114 *pchan = chan;
115
116 chan->id = -1;
117 chan->dev = dev;
118 chan->user_get = 4;
119 chan->user_put = 0;
120
121 ret = nouveau_gpuobj_new(dev, NULL, 32768, 0x1000,
122 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
123 if (ret) {
124 NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
125 nv50_evo_channel_del(pchan);
126 return ret;
127 }
128
129 ret = drm_mm_init(&chan->ramin_heap, 0, 32768);
130 if (ret) {
131 NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
132 nv50_evo_channel_del(pchan);
133 return ret;
134 }
135
136 ret = nouveau_gpuobj_new(dev, chan, 4096, 16, 0, &ramht);
137 if (ret) {
138 NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
139 nv50_evo_channel_del(pchan);
140 return ret;
141 }
142
143 ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
144 nouveau_gpuobj_ref(NULL, &ramht);
145 if (ret) {
146 nv50_evo_channel_del(pchan);
147 return ret;
148 }
149
150 if (dev_priv->chipset != 0x50) {
151 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB16, 0x70, 0x19,
152 0, 0xffffffff);
153 if (ret) {
154 nv50_evo_channel_del(pchan);
155 return ret;
156 }
157
158
159 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoFB32, 0x7a, 0x19,
160 0, 0xffffffff);
161 if (ret) {
162 nv50_evo_channel_del(pchan);
163 return ret;
164 }
165 }
166
167 ret = nv50_evo_dmaobj_new(chan, 0x3d, NvEvoVRAM, 0, 0x19,
168 0, dev_priv->vram_size);
169 if (ret) {
170 nv50_evo_channel_del(pchan);
171 return ret;
172 }
173
174 ret = nouveau_bo_new(dev, NULL, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0,
175 false, true, &chan->pushbuf_bo);
176 if (ret == 0)
177 ret = nouveau_bo_pin(chan->pushbuf_bo, TTM_PL_FLAG_VRAM);
178 if (ret) {
179 NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
180 nv50_evo_channel_del(pchan);
181 return ret;
182 }
183
184 ret = nouveau_bo_map(chan->pushbuf_bo);
185 if (ret) {
186 NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
187 nv50_evo_channel_del(pchan);
188 return ret;
189 }
190
191 chan->user = ioremap(pci_resource_start(dev->pdev, 0) +
192 NV50_PDISPLAY_USER(0), PAGE_SIZE);
193 if (!chan->user) {
194 NV_ERROR(dev, "Error mapping EVO control regs.\n");
195 nv50_evo_channel_del(pchan);
196 return -ENOMEM;
197 }
198
199 return 0;
200}
201
202int 49int
203nv50_display_early_init(struct drm_device *dev) 50nv50_display_early_init(struct drm_device *dev)
204{ 51{
@@ -214,12 +61,10 @@ int
214nv50_display_init(struct drm_device *dev) 61nv50_display_init(struct drm_device *dev)
215{ 62{
216 struct drm_nouveau_private *dev_priv = dev->dev_private; 63 struct drm_nouveau_private *dev_priv = dev->dev_private;
217 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
218 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; 64 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
219 struct nouveau_channel *evo = dev_priv->evo;
220 struct drm_connector *connector; 65 struct drm_connector *connector;
66 struct nouveau_channel *evo;
221 int ret, i; 67 int ret, i;
222 u64 start;
223 u32 val; 68 u32 val;
224 69
225 NV_DEBUG_KMS(dev, "\n"); 70 NV_DEBUG_KMS(dev, "\n");
@@ -303,7 +148,6 @@ nv50_display_init(struct drm_device *dev)
303 } 148 }
304 } 149 }
305 150
306 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
307 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000); 151 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
308 nv_wr32(dev, 0x610028, 0x00000000); 152 nv_wr32(dev, 0x610028, 0x00000000);
309 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000); 153 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
@@ -323,69 +167,12 @@ nv50_display_init(struct drm_device *dev)
323 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true); 167 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
324 } 168 }
325 169
326 /* taken from nv bug #12637, attempts to un-wedge the hw if it's 170 ret = nv50_evo_init(dev);
327 * stuck in some unspecified state
328 */
329 start = ptimer->read(dev);
330 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x2b00);
331 while ((val = nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0))) & 0x1e0000) {
332 if ((val & 0x9f0000) == 0x20000)
333 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
334 val | 0x800000);
335
336 if ((val & 0x3f0000) == 0x30000)
337 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
338 val | 0x200000);
339
340 if (ptimer->read(dev) - start > 1000000000ULL) {
341 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) != 0\n");
342 NV_ERROR(dev, "0x610200 = 0x%08x\n", val);
343 return -EBUSY;
344 }
345 }
346
347 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1000b03);
348 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
349 0x40000000, 0x40000000)) {
350 NV_ERROR(dev, "timeout: (0x610200 & 0x40000000) == 0x40000000\n");
351 NV_ERROR(dev, "0x610200 = 0x%08x\n",
352 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
353 return -EBUSY;
354 }
355
356 /* initialise fifo */
357 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_DMA_CB(0),
358 ((evo->pushbuf_bo->bo.mem.start << PAGE_SHIFT) >> 8) |
359 NV50_PDISPLAY_CHANNEL_DMA_CB_LOCATION_VRAM |
360 NV50_PDISPLAY_CHANNEL_DMA_CB_VALID);
361 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK2(0), 0x00010000);
362 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_UNK3(0), 0x00000002);
363 if (!nv_wait(dev, 0x610200, 0x80000000, 0x00000000)) {
364 NV_ERROR(dev, "timeout: (0x610200 & 0x80000000) == 0\n");
365 NV_ERROR(dev, "0x610200 = 0x%08x\n", nv_rd32(dev, 0x610200));
366 return -EBUSY;
367 }
368 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0),
369 (nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)) & ~0x00000003) |
370 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
371 nv_wr32(dev, NV50_PDISPLAY_USER_PUT(0), 0);
372 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x01000003 |
373 NV50_PDISPLAY_CHANNEL_STAT_DMA_ENABLED);
374
375 /* enable error reporting on the channel */
376 nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << 0);
377
378 evo->dma.max = (4096/4) - 2;
379 evo->dma.put = 0;
380 evo->dma.cur = evo->dma.put;
381 evo->dma.free = evo->dma.max - evo->dma.cur;
382
383 ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
384 if (ret) 171 if (ret)
385 return ret; 172 return ret;
173 evo = dev_priv->evo;
386 174
387 for (i = 0; i < NOUVEAU_DMA_SKIPS; i++) 175 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
388 OUT_RING(evo, 0);
389 176
390 ret = RING_SPACE(evo, 11); 177 ret = RING_SPACE(evo, 11);
391 if (ret) 178 if (ret)
@@ -449,12 +236,7 @@ static int nv50_display_disable(struct drm_device *dev)
449 } 236 }
450 } 237 }
451 238
452 nv_wr32(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0); 239 nv50_evo_fini(dev);
453 if (!nv_wait(dev, NV50_PDISPLAY_CHANNEL_STAT(0), 0x1e0000, 0)) {
454 NV_ERROR(dev, "timeout: (0x610200 & 0x1e0000) == 0\n");
455 NV_ERROR(dev, "0x610200 = 0x%08x\n",
456 nv_rd32(dev, NV50_PDISPLAY_CHANNEL_STAT(0)));
457 }
458 240
459 for (i = 0; i < 3; i++) { 241 for (i = 0; i < 3; i++) {
460 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i), 242 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
@@ -504,13 +286,6 @@ int nv50_display_create(struct drm_device *dev)
504 286
505 dev->mode_config.fb_base = dev_priv->fb_phys; 287 dev->mode_config.fb_base = dev_priv->fb_phys;
506 288
507 /* Create EVO channel */
508 ret = nv50_evo_channel_new(dev, &dev_priv->evo);
509 if (ret) {
510 NV_ERROR(dev, "Error creating EVO channel: %d\n", ret);
511 return ret;
512 }
513
514 /* Create CRTC objects */ 289 /* Create CRTC objects */
515 for (i = 0; i < 2; i++) 290 for (i = 0; i < 2; i++)
516 nv50_crtc_create(dev, i); 291 nv50_crtc_create(dev, i);
@@ -565,14 +340,11 @@ int nv50_display_create(struct drm_device *dev)
565void 340void
566nv50_display_destroy(struct drm_device *dev) 341nv50_display_destroy(struct drm_device *dev)
567{ 342{
568 struct drm_nouveau_private *dev_priv = dev->dev_private;
569
570 NV_DEBUG_KMS(dev, "\n"); 343 NV_DEBUG_KMS(dev, "\n");
571 344
572 drm_mode_config_cleanup(dev); 345 drm_mode_config_cleanup(dev);
573 346
574 nv50_display_disable(dev); 347 nv50_display_disable(dev);
575 nv50_evo_channel_del(&dev_priv->evo);
576} 348}
577 349
578static u16 350static u16