drm/nouveau: remove ability to use external firmware

This was always really a developer option, and if it's really necessary we
can hack this in ourselves.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

1 files changed, 20 insertions, 34 deletions

diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index 2608c34eca82..fd7d2b501316 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -58,6 +58,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+        struct nouveau_grctx ctx = {};
         int ret;
 
         ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
@@ -67,16 +68,11 @@ nv40_graph_create_context(struct nouveau_channel *chan)
                 return ret;
 
         /* Initialise default context values */
-        if (!pgraph->ctxprog) {
-                struct nouveau_grctx ctx = {};
+        ctx.dev = chan->dev;
+        ctx.mode = NOUVEAU_GRCTX_VALS;
+        ctx.data = chan->ramin_grctx->gpuobj;
+        nv40_grctx_init(&ctx);
 
-                ctx.dev = chan->dev;
-                ctx.mode = NOUVEAU_GRCTX_VALS;
-                ctx.data = chan->ramin_grctx->gpuobj;
-                nv40_grctx_init(&ctx);
-        } else {
-                nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
-        }
         nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
                      chan->ramin_grctx->gpuobj->im_pramin->start);
         return 0;
@@ -236,7 +232,8 @@ nv40_graph_init(struct drm_device *dev)
         struct drm_nouveau_private *dev_priv =
                 (struct drm_nouveau_private *)dev->dev_private;
         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
-        uint32_t vramsz;
+        struct nouveau_grctx ctx = {};
+        uint32_t vramsz, *cp;
         int i, j;
 
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -244,32 +241,22 @@ nv40_graph_init(struct drm_device *dev)
         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
                          NV_PMC_ENABLE_PGRAPH);
 
-        if (nouveau_ctxfw) {
-                nouveau_grctx_prog_load(dev);
-                dev_priv->engine.graph.grctx_size = 175 * 1024;
-        }
-
-        if (!dev_priv->engine.graph.ctxprog) {
-                struct nouveau_grctx ctx = {};
-                uint32_t *cp;
-
-                cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
-                if (!cp)
-                        return -ENOMEM;
+        cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
+        if (!cp)
+                return -ENOMEM;
 
-                ctx.dev = dev;
-                ctx.mode = NOUVEAU_GRCTX_PROG;
-                ctx.data = cp;
-                ctx.ctxprog_max = 256;
-                nv40_grctx_init(&ctx);
-                dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
+        ctx.dev = dev;
+        ctx.mode = NOUVEAU_GRCTX_PROG;
+        ctx.data = cp;
+        ctx.ctxprog_max = 256;
+        nv40_grctx_init(&ctx);
+        dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
 
-                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
-                for (i = 0; i < ctx.ctxprog_len; i++)
-                        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
+        nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+        for (i = 0; i < ctx.ctxprog_len; i++)
+                nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
 
-                kfree(cp);
-        }
+        kfree(cp);
 
         /* No context present currently */
         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -405,7 +392,6 @@ nv40_graph_init(struct drm_device *dev)
 
 void nv40_graph_takedown(struct drm_device *dev)
 {
-        nouveau_grctx_fini(dev);
 }
 
 struct nouveau_pgraph_object_class nv40_graph_grclass[] = {