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authorBen Skeggs <bskeggs@redhat.com>2010-09-01 01:24:31 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-09-24 02:20:14 -0400
commita8eaebc6c52bb0cd243b4cb421068f42d378be9c (patch)
tree12f796e5210d51f78b9fc6ddd4750cf1421373c2 /drivers/gpu/drm/nouveau/nv20_graph.c
parentde3a6c0a3b642c0c350414d63298a1b19a009290 (diff)
drm/nouveau: remove nouveau_gpuobj_ref completely, replace with sanity
Reviewed-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv20_graph.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv20_graph.c40
1 files changed, 18 insertions, 22 deletions
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index d8693d32bd0e..12ab9cd56eca 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -403,21 +403,19 @@ nv20_graph_create_context(struct nouveau_channel *chan)
403 BUG_ON(1); 403 BUG_ON(1);
404 } 404 }
405 405
406 ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size, 406 ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
407 16, NVOBJ_FLAG_ZERO_ALLOC, 407 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
408 &chan->ramin_grctx);
409 if (ret) 408 if (ret)
410 return ret; 409 return ret;
411 410
412 /* Initialise default context values */ 411 /* Initialise default context values */
413 ctx_init(dev, chan->ramin_grctx->gpuobj); 412 ctx_init(dev, chan->ramin_grctx);
414 413
415 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */ 414 /* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
416 nv_wo32(chan->ramin_grctx->gpuobj, idoffs, 415 nv_wo32(chan->ramin_grctx, idoffs,
417 (chan->id << 24) | 0x1); /* CTX_USER */ 416 (chan->id << 24) | 0x1); /* CTX_USER */
418 417
419 nv_wo32(pgraph->ctx_table->gpuobj, chan->id * 4, 418 nv_wo32(pgraph->ctx_table, chan->id * 4, chan->ramin_grctx->pinst >> 4);
420 chan->ramin_grctx->instance >> 4);
421 return 0; 419 return 0;
422} 420}
423 421
@@ -428,10 +426,8 @@ nv20_graph_destroy_context(struct nouveau_channel *chan)
428 struct drm_nouveau_private *dev_priv = dev->dev_private; 426 struct drm_nouveau_private *dev_priv = dev->dev_private;
429 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 427 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
430 428
431 if (chan->ramin_grctx) 429 nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
432 nouveau_gpuobj_ref_del(dev, &chan->ramin_grctx); 430 nv_wo32(pgraph->ctx_table, chan->id * 4, 0);
433
434 nv_wo32(pgraph->ctx_table->gpuobj, chan->id * 4, 0);
435} 431}
436 432
437int 433int
@@ -442,7 +438,7 @@ nv20_graph_load_context(struct nouveau_channel *chan)
442 438
443 if (!chan->ramin_grctx) 439 if (!chan->ramin_grctx)
444 return -EINVAL; 440 return -EINVAL;
445 inst = chan->ramin_grctx->instance >> 4; 441 inst = chan->ramin_grctx->pinst >> 4;
446 442
447 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 443 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
448 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, 444 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
@@ -465,7 +461,7 @@ nv20_graph_unload_context(struct drm_device *dev)
465 chan = pgraph->channel(dev); 461 chan = pgraph->channel(dev);
466 if (!chan) 462 if (!chan)
467 return 0; 463 return 0;
468 inst = chan->ramin_grctx->instance >> 4; 464 inst = chan->ramin_grctx->pinst >> 4;
469 465
470 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); 466 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
471 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER, 467 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
@@ -552,15 +548,15 @@ nv20_graph_init(struct drm_device *dev)
552 548
553 if (!pgraph->ctx_table) { 549 if (!pgraph->ctx_table) {
554 /* Create Context Pointer Table */ 550 /* Create Context Pointer Table */
555 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32 * 4, 16, 551 ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
556 NVOBJ_FLAG_ZERO_ALLOC, 552 NVOBJ_FLAG_ZERO_ALLOC,
557 &pgraph->ctx_table); 553 &pgraph->ctx_table);
558 if (ret) 554 if (ret)
559 return ret; 555 return ret;
560 } 556 }
561 557
562 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, 558 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
563 pgraph->ctx_table->instance >> 4); 559 pgraph->ctx_table->pinst >> 4);
564 560
565 nv20_graph_rdi(dev); 561 nv20_graph_rdi(dev);
566 562
@@ -646,7 +642,7 @@ nv20_graph_takedown(struct drm_device *dev)
646 struct drm_nouveau_private *dev_priv = dev->dev_private; 642 struct drm_nouveau_private *dev_priv = dev->dev_private;
647 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; 643 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
648 644
649 nouveau_gpuobj_ref_del(dev, &pgraph->ctx_table); 645 nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
650} 646}
651 647
652int 648int
@@ -681,15 +677,15 @@ nv30_graph_init(struct drm_device *dev)
681 677
682 if (!pgraph->ctx_table) { 678 if (!pgraph->ctx_table) {
683 /* Create Context Pointer Table */ 679 /* Create Context Pointer Table */
684 ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, 32 * 4, 16, 680 ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
685 NVOBJ_FLAG_ZERO_ALLOC, 681 NVOBJ_FLAG_ZERO_ALLOC,
686 &pgraph->ctx_table); 682 &pgraph->ctx_table);
687 if (ret) 683 if (ret)
688 return ret; 684 return ret;
689 } 685 }
690 686
691 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, 687 nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
692 pgraph->ctx_table->instance >> 4); 688 pgraph->ctx_table->pinst >> 4);
693 689
694 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); 690 nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
695 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF); 691 nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);