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authorBen Skeggs <bskeggs@redhat.com>2009-12-11 04:24:15 -0500
committerDave Airlie <airlied@redhat.com>2009-12-11 06:29:34 -0500
commit6ee738610f41b59733f63718f0bdbcba7d3a3f12 (patch)
treeeccb9f07671998c50a1bc606a54cd6f82ba43e0a /drivers/gpu/drm/nouveau/nv10_fifo.c
parentd1ede145cea25c5b6d2ebb19b167af14e374bb45 (diff)
drm/nouveau: Add DRM driver for NVIDIA GPUs
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Kościelnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fifo.c')
-rw-r--r--drivers/gpu/drm/nouveau/nv10_fifo.c260
1 files changed, 260 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fifo.c b/drivers/gpu/drm/nouveau/nv10_fifo.c
new file mode 100644
index 000000000000..7aeabf262bc0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv10_fifo.c
@@ -0,0 +1,260 @@
1/*
2 * Copyright (C) 2007 Ben Skeggs.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#include "drmP.h"
28#include "drm.h"
29#include "nouveau_drv.h"
30
31#define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE))
32#define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32)
33
34int
35nv10_fifo_channel_id(struct drm_device *dev)
36{
37 return nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH1) &
38 NV10_PFIFO_CACHE1_PUSH1_CHID_MASK;
39}
40
41int
42nv10_fifo_create_context(struct nouveau_channel *chan)
43{
44 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
45 struct drm_device *dev = chan->dev;
46 uint32_t fc = NV10_RAMFC(chan->id);
47 int ret;
48
49 ret = nouveau_gpuobj_new_fake(dev, NV10_RAMFC(chan->id), ~0,
50 NV10_RAMFC__SIZE, NVOBJ_FLAG_ZERO_ALLOC |
51 NVOBJ_FLAG_ZERO_FREE, NULL, &chan->ramfc);
52 if (ret)
53 return ret;
54
55 /* Fill entries that are seen filled in dumps of nvidia driver just
56 * after channel's is put into DMA mode
57 */
58 dev_priv->engine.instmem.prepare_access(dev, true);
59 nv_wi32(dev, fc + 0, chan->pushbuf_base);
60 nv_wi32(dev, fc + 4, chan->pushbuf_base);
61 nv_wi32(dev, fc + 12, chan->pushbuf->instance >> 4);
62 nv_wi32(dev, fc + 20, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
63 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
64 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
65#ifdef __BIG_ENDIAN
66 NV_PFIFO_CACHE1_BIG_ENDIAN |
67#endif
68 0);
69 dev_priv->engine.instmem.finish_access(dev);
70
71 /* enable the fifo dma operation */
72 nv_wr32(dev, NV04_PFIFO_MODE,
73 nv_rd32(dev, NV04_PFIFO_MODE) | (1 << chan->id));
74 return 0;
75}
76
77void
78nv10_fifo_destroy_context(struct nouveau_channel *chan)
79{
80 struct drm_device *dev = chan->dev;
81
82 nv_wr32(dev, NV04_PFIFO_MODE,
83 nv_rd32(dev, NV04_PFIFO_MODE) & ~(1 << chan->id));
84
85 nouveau_gpuobj_ref_del(dev, &chan->ramfc);
86}
87
88static void
89nv10_fifo_do_load_context(struct drm_device *dev, int chid)
90{
91 struct drm_nouveau_private *dev_priv = dev->dev_private;
92 uint32_t fc = NV10_RAMFC(chid), tmp;
93
94 dev_priv->engine.instmem.prepare_access(dev, false);
95
96 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUT, nv_ri32(dev, fc + 0));
97 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET, nv_ri32(dev, fc + 4));
98 nv_wr32(dev, NV10_PFIFO_CACHE1_REF_CNT, nv_ri32(dev, fc + 8));
99
100 tmp = nv_ri32(dev, fc + 12);
101 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE, tmp & 0xFFFF);
102 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT, tmp >> 16);
103
104 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, nv_ri32(dev, fc + 16));
105 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_FETCH, nv_ri32(dev, fc + 20));
106 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_ri32(dev, fc + 24));
107 nv_wr32(dev, NV04_PFIFO_CACHE1_PULL1, nv_ri32(dev, fc + 28));
108
109 if (dev_priv->chipset < 0x17)
110 goto out;
111
112 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE, nv_ri32(dev, fc + 32));
113 tmp = nv_ri32(dev, fc + 36);
114 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP, tmp);
115 nv_wr32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT, nv_ri32(dev, fc + 40));
116 nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, nv_ri32(dev, fc + 44));
117 nv_wr32(dev, NV10_PFIFO_CACHE1_DMA_SUBROUTINE, nv_ri32(dev, fc + 48));
118
119out:
120 dev_priv->engine.instmem.finish_access(dev);
121
122 nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
123 nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
124}
125
126int
127nv10_fifo_load_context(struct nouveau_channel *chan)
128{
129 struct drm_device *dev = chan->dev;
130 uint32_t tmp;
131
132 nv10_fifo_do_load_context(dev, chan->id);
133
134 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
135 NV03_PFIFO_CACHE1_PUSH1_DMA | chan->id);
136 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 1);
137
138 /* Reset NV04_PFIFO_CACHE1_DMA_CTL_AT_INFO to INVALID */
139 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_CTL) & ~(1 << 31);
140 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_CTL, tmp);
141
142 return 0;
143}
144
145int
146nv10_fifo_unload_context(struct drm_device *dev)
147{
148 struct drm_nouveau_private *dev_priv = dev->dev_private;
149 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
150 uint32_t fc, tmp;
151 int chid;
152
153 chid = pfifo->channel_id(dev);
154 if (chid < 0 || chid >= dev_priv->engine.fifo.channels)
155 return 0;
156 fc = NV10_RAMFC(chid);
157
158 dev_priv->engine.instmem.prepare_access(dev, true);
159
160 nv_wi32(dev, fc + 0, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT));
161 nv_wi32(dev, fc + 4, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
162 nv_wi32(dev, fc + 8, nv_rd32(dev, NV10_PFIFO_CACHE1_REF_CNT));
163 tmp = nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_INSTANCE) & 0xFFFF;
164 tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_DCOUNT) << 16);
165 nv_wi32(dev, fc + 12, tmp);
166 nv_wi32(dev, fc + 16, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_STATE));
167 nv_wi32(dev, fc + 20, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_FETCH));
168 nv_wi32(dev, fc + 24, nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE));
169 nv_wi32(dev, fc + 28, nv_rd32(dev, NV04_PFIFO_CACHE1_PULL1));
170
171 if (dev_priv->chipset < 0x17)
172 goto out;
173
174 nv_wi32(dev, fc + 32, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_VALUE));
175 tmp = nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP);
176 nv_wi32(dev, fc + 36, tmp);
177 nv_wi32(dev, fc + 40, nv_rd32(dev, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT));
178 nv_wi32(dev, fc + 44, nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE));
179 nv_wi32(dev, fc + 48, nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_GET));
180
181out:
182 dev_priv->engine.instmem.finish_access(dev);
183
184 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
185 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
186 return 0;
187}
188
189static void
190nv10_fifo_init_reset(struct drm_device *dev)
191{
192 nv_wr32(dev, NV03_PMC_ENABLE,
193 nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PFIFO);
194 nv_wr32(dev, NV03_PMC_ENABLE,
195 nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PFIFO);
196
197 nv_wr32(dev, 0x003224, 0x000f0078);
198 nv_wr32(dev, 0x002044, 0x0101ffff);
199 nv_wr32(dev, 0x002040, 0x000000ff);
200 nv_wr32(dev, 0x002500, 0x00000000);
201 nv_wr32(dev, 0x003000, 0x00000000);
202 nv_wr32(dev, 0x003050, 0x00000000);
203
204 nv_wr32(dev, 0x003258, 0x00000000);
205 nv_wr32(dev, 0x003210, 0x00000000);
206 nv_wr32(dev, 0x003270, 0x00000000);
207}
208
209static void
210nv10_fifo_init_ramxx(struct drm_device *dev)
211{
212 struct drm_nouveau_private *dev_priv = dev->dev_private;
213
214 nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ |
215 ((dev_priv->ramht_bits - 9) << 16) |
216 (dev_priv->ramht_offset >> 8));
217 nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8);
218
219 if (dev_priv->chipset < 0x17) {
220 nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8);
221 } else {
222 nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset >> 8) |
223 (1 << 16) /* 64 Bytes entry*/);
224 /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */
225 }
226}
227
228static void
229nv10_fifo_init_intr(struct drm_device *dev)
230{
231 nv_wr32(dev, 0x002100, 0xffffffff);
232 nv_wr32(dev, 0x002140, 0xffffffff);
233}
234
235int
236nv10_fifo_init(struct drm_device *dev)
237{
238 struct drm_nouveau_private *dev_priv = dev->dev_private;
239 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
240 int i;
241
242 nv10_fifo_init_reset(dev);
243 nv10_fifo_init_ramxx(dev);
244
245 nv10_fifo_do_load_context(dev, pfifo->channels - 1);
246 nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, pfifo->channels - 1);
247
248 nv10_fifo_init_intr(dev);
249 pfifo->enable(dev);
250 pfifo->reassign(dev, true);
251
252 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
253 if (dev_priv->fifos[i]) {
254 uint32_t mode = nv_rd32(dev, NV04_PFIFO_MODE);
255 nv_wr32(dev, NV04_PFIFO_MODE, mode | (1 << i));
256 }
257 }
258
259 return 0;
260}
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-22 18:38:13 -0400