diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-09-01 01:24:35 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-09-24 02:23:22 -0400 |
commit | e05c5a317efb03854950a3fcc5c9501bfefc7d68 (patch) | |
tree | 188a3d497848cd383e69734a17e4d76f7939056f /drivers/gpu/drm/nouveau/nv10_fifo.c | |
parent | fbd2895e45aebdb3d3ea73a3a796cf3bb9c912da (diff) |
drm/nouveau: tidy ram{ht,fc,ro} a bit
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv10_fifo.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv10_fifo.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/drivers/gpu/drm/nouveau/nv10_fifo.c b/drivers/gpu/drm/nouveau/nv10_fifo.c index ccb07fb701ca..f1b03ad58fd5 100644 --- a/drivers/gpu/drm/nouveau/nv10_fifo.c +++ b/drivers/gpu/drm/nouveau/nv10_fifo.c | |||
@@ -27,8 +27,9 @@ | |||
27 | #include "drmP.h" | 27 | #include "drmP.h" |
28 | #include "drm.h" | 28 | #include "drm.h" |
29 | #include "nouveau_drv.h" | 29 | #include "nouveau_drv.h" |
30 | #include "nouveau_ramht.h" | ||
30 | 31 | ||
31 | #define NV10_RAMFC(c) (dev_priv->ramfc_offset + ((c) * NV10_RAMFC__SIZE)) | 32 | #define NV10_RAMFC(c) (dev_priv->ramfc->pinst + ((c) * NV10_RAMFC__SIZE)) |
32 | #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) | 33 | #define NV10_RAMFC__SIZE ((dev_priv->chipset) >= 0x17 ? 64 : 32) |
33 | 34 | ||
34 | int | 35 | int |
@@ -202,14 +203,14 @@ nv10_fifo_init_ramxx(struct drm_device *dev) | |||
202 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 203 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
203 | 204 | ||
204 | nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | | 205 | nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
205 | ((dev_priv->ramht_bits - 9) << 16) | | 206 | ((dev_priv->ramht->bits - 9) << 16) | |
206 | (dev_priv->ramht_offset >> 8)); | 207 | (dev_priv->ramht->gpuobj->pinst >> 8)); |
207 | nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro_offset>>8); | 208 | nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8); |
208 | 209 | ||
209 | if (dev_priv->chipset < 0x17) { | 210 | if (dev_priv->chipset < 0x17) { |
210 | nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc_offset >> 8); | 211 | nv_wr32(dev, NV03_PFIFO_RAMFC, dev_priv->ramfc->pinst >> 8); |
211 | } else { | 212 | } else { |
212 | nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc_offset >> 8) | | 213 | nv_wr32(dev, NV03_PFIFO_RAMFC, (dev_priv->ramfc->pinst >> 8) | |
213 | (1 << 16) /* 64 Bytes entry*/); | 214 | (1 << 16) /* 64 Bytes entry*/); |
214 | /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */ | 215 | /* XXX nvidia blob set bit 18, 21,23 for nv20 & nv30 */ |
215 | } | 216 | } |