diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2012-05-01 06:48:08 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2012-05-24 02:56:11 -0400 |
commit | c420b2dc8dc3cdd507214f4df5c5f96f08812cbe (patch) | |
tree | 6dca9f0aba3de22a2bda5fe647d6945d4f4e986e /drivers/gpu/drm/nouveau/nv04_instmem.c | |
parent | a226c32a386bca0426e500954b79e3fd46afc0d9 (diff) |
drm/nouveau/fifo: turn all fifo modules into engine modules
Been tested on each major revision that's relevant here, but I'm sure there
are still bugs waiting to be ironed out.
This is a *very* invasive change.
There's a couple of pieces left that I don't like much (eg. other engines
using fifo_priv for the channel count), but that's an artefact of there
being a master channel list still. This is changing, slowly.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nv04_instmem.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nv04_instmem.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c index 1acc626f74b0..ef7a934a499a 100644 --- a/drivers/gpu/drm/nouveau/nv04_instmem.c +++ b/drivers/gpu/drm/nouveau/nv04_instmem.c | |||
@@ -1,6 +1,8 @@ | |||
1 | #include "drmP.h" | 1 | #include "drmP.h" |
2 | #include "drm.h" | 2 | #include "drm.h" |
3 | |||
3 | #include "nouveau_drv.h" | 4 | #include "nouveau_drv.h" |
5 | #include "nouveau_fifo.h" | ||
4 | #include "nouveau_ramht.h" | 6 | #include "nouveau_ramht.h" |
5 | 7 | ||
6 | /* returns the size of fifo context */ | 8 | /* returns the size of fifo context */ |
@@ -10,12 +12,15 @@ nouveau_fifo_ctx_size(struct drm_device *dev) | |||
10 | struct drm_nouveau_private *dev_priv = dev->dev_private; | 12 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
11 | 13 | ||
12 | if (dev_priv->chipset >= 0x40) | 14 | if (dev_priv->chipset >= 0x40) |
13 | return 128; | 15 | return 128 * 32; |
14 | else | 16 | else |
15 | if (dev_priv->chipset >= 0x17) | 17 | if (dev_priv->chipset >= 0x17) |
16 | return 64; | 18 | return 64 * 32; |
19 | else | ||
20 | if (dev_priv->chipset >= 0x10) | ||
21 | return 32 * 32; | ||
17 | 22 | ||
18 | return 32; | 23 | return 32 * 16; |
19 | } | 24 | } |
20 | 25 | ||
21 | int nv04_instmem_init(struct drm_device *dev) | 26 | int nv04_instmem_init(struct drm_device *dev) |
@@ -39,7 +44,7 @@ int nv04_instmem_init(struct drm_device *dev) | |||
39 | else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; | 44 | else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs; |
40 | else rsvd = 0x4a40 * vs; | 45 | else rsvd = 0x4a40 * vs; |
41 | rsvd += 16 * 1024; | 46 | rsvd += 16 * 1024; |
42 | rsvd *= dev_priv->engine.fifo.channels; | 47 | rsvd *= 32; /* per-channel */ |
43 | 48 | ||
44 | rsvd += 512 * 1024; /* pci(e)gart table */ | 49 | rsvd += 512 * 1024; /* pci(e)gart table */ |
45 | rsvd += 512 * 1024; /* object storage */ | 50 | rsvd += 512 * 1024; /* object storage */ |
@@ -67,7 +72,7 @@ int nv04_instmem_init(struct drm_device *dev) | |||
67 | return ret; | 72 | return ret; |
68 | 73 | ||
69 | /* And RAMFC */ | 74 | /* And RAMFC */ |
70 | length = dev_priv->engine.fifo.channels * nouveau_fifo_ctx_size(dev); | 75 | length = nouveau_fifo_ctx_size(dev); |
71 | switch (dev_priv->card_type) { | 76 | switch (dev_priv->card_type) { |
72 | case NV_40: | 77 | case NV_40: |
73 | offset = 0x20000; | 78 | offset = 0x20000; |