diff options
author | Ben Skeggs <bskeggs@redhat.com> | 2010-07-07 23:15:05 -0400 |
---|---|---|
committer | Ben Skeggs <bskeggs@redhat.com> | 2010-07-12 20:13:44 -0400 |
commit | 816544b21b020bdb9dcb9a5003fe3e1f109e8698 (patch) | |
tree | 9900fe739b77e0025da23b4a694a1f40d453f857 /drivers/gpu/drm/nouveau/nouveau_object.c | |
parent | ec91db269e6a3c7f45b96169ccf5dbd1fde8fce8 (diff) |
drm/nouveau: allocate fixed amount of PRAMIN per channel on all chipsets
Previously only done on nv50+
This commit also switches unknown NV2x/NV3x chipsets to noaccel mode.
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_object.c')
-rw-r--r-- | drivers/gpu/drm/nouveau/nouveau_object.c | 36 |
1 files changed, 8 insertions, 28 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c index 7d86e05ac883..b6bcb254f4ab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_object.c +++ b/drivers/gpu/drm/nouveau/nouveau_object.c | |||
@@ -229,25 +229,12 @@ nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, | |||
229 | * available. | 229 | * available. |
230 | */ | 230 | */ |
231 | if (chan) { | 231 | if (chan) { |
232 | if (chan->ramin_heap.ml_entry.next) { | 232 | NV_DEBUG(dev, "channel heap\n"); |
233 | NV_DEBUG(dev, "private heap\n"); | 233 | pramin = &chan->ramin_heap; |
234 | pramin = &chan->ramin_heap; | ||
235 | } else | ||
236 | if (dev_priv->card_type < NV_50) { | ||
237 | NV_DEBUG(dev, "global heap fallback\n"); | ||
238 | pramin = &dev_priv->ramin_heap; | ||
239 | } | ||
240 | } else { | 234 | } else { |
241 | NV_DEBUG(dev, "global heap\n"); | 235 | NV_DEBUG(dev, "global heap\n"); |
242 | pramin = &dev_priv->ramin_heap; | 236 | pramin = &dev_priv->ramin_heap; |
243 | } | ||
244 | |||
245 | if (!pramin) { | ||
246 | NV_ERROR(dev, "No PRAMIN heap!\n"); | ||
247 | return -EINVAL; | ||
248 | } | ||
249 | 237 | ||
250 | if (!chan) { | ||
251 | ret = engine->instmem.populate(dev, gpuobj, &size); | 238 | ret = engine->instmem.populate(dev, gpuobj, &size); |
252 | if (ret) { | 239 | if (ret) { |
253 | nouveau_gpuobj_del(dev, &gpuobj); | 240 | nouveau_gpuobj_del(dev, &gpuobj); |
@@ -911,6 +898,7 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |||
911 | base = 0; | 898 | base = 0; |
912 | 899 | ||
913 | /* PGRAPH context */ | 900 | /* PGRAPH context */ |
901 | size += dev_priv->engine.graph.grctx_size; | ||
914 | 902 | ||
915 | if (dev_priv->card_type == NV_50) { | 903 | if (dev_priv->card_type == NV_50) { |
916 | /* Various fixed table thingos */ | 904 | /* Various fixed table thingos */ |
@@ -921,12 +909,8 @@ nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |||
921 | size += 0x8000; | 909 | size += 0x8000; |
922 | /* RAMFC */ | 910 | /* RAMFC */ |
923 | size += 0x1000; | 911 | size += 0x1000; |
924 | /* PGRAPH context */ | ||
925 | size += 0x70000; | ||
926 | } | 912 | } |
927 | 913 | ||
928 | NV_DEBUG(dev, "ch%d PRAMIN size: 0x%08x bytes, base alloc=0x%08x\n", | ||
929 | chan->id, size, base); | ||
930 | ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0, | 914 | ret = nouveau_gpuobj_new_ref(dev, NULL, NULL, 0, size, 0x1000, 0, |
931 | &chan->ramin); | 915 | &chan->ramin); |
932 | if (ret) { | 916 | if (ret) { |
@@ -959,15 +943,11 @@ nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |||
959 | 943 | ||
960 | NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); | 944 | NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); |
961 | 945 | ||
962 | /* Reserve a block of PRAMIN for the channel | 946 | /* Allocate a chunk of memory for per-channel object storage */ |
963 | *XXX: maybe on <NV50 too at some point | 947 | ret = nouveau_gpuobj_channel_init_pramin(chan); |
964 | */ | 948 | if (ret) { |
965 | if (0 || dev_priv->card_type == NV_50) { | 949 | NV_ERROR(dev, "init pramin\n"); |
966 | ret = nouveau_gpuobj_channel_init_pramin(chan); | 950 | return ret; |
967 | if (ret) { | ||
968 | NV_ERROR(dev, "init pramin\n"); | ||
969 | return ret; | ||
970 | } | ||
971 | } | 951 | } |
972 | 952 | ||
973 | /* NV50 VM | 953 | /* NV50 VM |