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authorBen Skeggs <bskeggs@redhat.com>2010-10-21 00:07:03 -0400
committerBen Skeggs <bskeggs@redhat.com>2010-12-03 00:11:03 -0500
commit35fa2f2ad161024e735fb0cd571cb92e50171afd (patch)
treee6c45b234f2af49d0a4fb4634954042daa64c06e /drivers/gpu/drm/nouveau/nouveau_irq.c
parent01d63187d1aad6236dd229d5824c61a60f1ab42c (diff)
drm/nouveau: add support for MSI
Only supported on NV50+ so far, and disabled by default currently. The module parameter "msi=1" will enable it. There's a kernel bug which will cause this to fail if the module (or the NVIDIA binary driver) has ever been loaded before loading nouveau with MSI enabled. As such, this is only safe to enable if you have nouveau load on boot, and don't wish to ever reload it. The workaround is to "echo 0 > /sys/bus/pci/devices/<device>/enable" until the enable count reads 0. Then you should be able to load nouveau with MSI enabled. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_irq.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_irq.c35
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_irq.c b/drivers/gpu/drm/nouveau/nouveau_irq.c
index ca9b969f4f9c..17e2fa86cde7 100644
--- a/drivers/gpu/drm/nouveau/nouveau_irq.c
+++ b/drivers/gpu/drm/nouveau/nouveau_irq.c
@@ -68,8 +68,13 @@ nouveau_irq_preinstall(struct drm_device *dev)
68int 68int
69nouveau_irq_postinstall(struct drm_device *dev) 69nouveau_irq_postinstall(struct drm_device *dev)
70{ 70{
71 struct drm_nouveau_private *dev_priv = dev->dev_private;
72
71 /* Master enable */ 73 /* Master enable */
72 nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE); 74 nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
75 if (dev_priv->msi_enabled)
76 nv_wr08(dev, 0x00088068, 0xff);
77
73 return 0; 78 return 0;
74} 79}
75 80
@@ -1263,5 +1268,35 @@ nouveau_irq_handler(DRM_IRQ_ARGS)
1263 1268
1264 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); 1269 spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
1265 1270
1271 if (dev_priv->msi_enabled)
1272 nv_wr08(dev, 0x00088068, 0xff);
1273
1266 return IRQ_HANDLED; 1274 return IRQ_HANDLED;
1267} 1275}
1276
1277int
1278nouveau_irq_init(struct drm_device *dev)
1279{
1280 struct drm_nouveau_private *dev_priv = dev->dev_private;
1281 int ret;
1282
1283 if (nouveau_msi != 0 && dev_priv->card_type >= NV_50) {
1284 ret = pci_enable_msi(dev->pdev);
1285 if (ret == 0) {
1286 NV_INFO(dev, "enabled MSI\n");
1287 dev_priv->msi_enabled = true;
1288 }
1289 }
1290
1291 return drm_irq_install(dev);
1292}
1293
1294void
1295nouveau_irq_fini(struct drm_device *dev)
1296{
1297 struct drm_nouveau_private *dev_priv = dev->dev_private;
1298
1299 drm_irq_uninstall(dev);
1300 if (dev_priv->msi_enabled)
1301 pci_disable_msi(dev->pdev);
1302}