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authorBen Skeggs <bskeggs@redhat.com>2009-12-11 04:24:15 -0500
committerDave Airlie <airlied@redhat.com>2009-12-11 06:29:34 -0500
commit6ee738610f41b59733f63718f0bdbcba7d3a3f12 (patch)
treeeccb9f07671998c50a1bc606a54cd6f82ba43e0a /drivers/gpu/drm/nouveau/nouveau_hw.c
parentd1ede145cea25c5b6d2ebb19b167af14e374bb45 (diff)
drm/nouveau: Add DRM driver for NVIDIA GPUs
This adds a drm/kms staging non-API stable driver for GPUs from NVIDIA. This driver is a KMS-based driver and requires a compatible nouveau userspace libdrm and nouveau X.org driver. This driver requires firmware files not available in this kernel tree, interested parties can find them via the nouveau project git archive. This driver is reverse engineered, and is in no way supported by nVidia. Support for nearly the complete range of nvidia hw from nv04->g80 (nv50) is available, and the kms driver should support driving nearly all output types (displayport is under development still) along with supporting suspend/resume. This work is all from the upstream nouveau project found at nouveau.freedesktop.org. The original authors list from nouveau git tree is: Anssi Hannula <anssi.hannula@iki.fi> Ben Skeggs <bskeggs@redhat.com> Francisco Jerez <currojerez@riseup.net> Maarten Maathuis <madman2003@gmail.com> Marcin Kościelnicki <koriakin@0x04.net> Matthew Garrett <mjg@redhat.com> Matt Parnell <mparnell@gmail.com> Patrice Mandin <patmandin@gmail.com> Pekka Paalanen <pq@iki.fi> Xavier Chantry <shiningxc@gmail.com> along with project founder Stephane Marchesin <marchesin@icps.u-strasbg.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_hw.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_hw.c1080
1 files changed, 1080 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
new file mode 100644
index 000000000000..dc46792a5c96
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -0,0 +1,1080 @@
1/*
2 * Copyright 2006 Dave Airlie
3 * Copyright 2007 Maarten Maathuis
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#include "nouveau_drv.h"
27#include "nouveau_hw.h"
28
29#define CHIPSET_NFORCE 0x01a0
30#define CHIPSET_NFORCE2 0x01f0
31
32/*
33 * misc hw access wrappers/control functions
34 */
35
36void
37NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
38{
39 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
40 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
41}
42
43uint8_t
44NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
45{
46 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
47 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
48}
49
50void
51NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
52{
53 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
54 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
55}
56
57uint8_t
58NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
59{
60 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
61 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
62}
63
64/* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
65 * it affects only the 8 bit vga io regs, which we access using mmio at
66 * 0xc{0,2}3c*, 0x60{1,3}3*, and 0x68{1,3}3d*
67 * in general, the set value of cr44 does not matter: reg access works as
68 * expected and values can be set for the appropriate head by using a 0x2000
69 * offset as required
70 * however:
71 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
72 * cr44 must be set to 0 or 3 for accessing values on the correct head
73 * through the common 0xc03c* addresses
74 * b) in tied mode (4) head B is programmed to the values set on head A, and
75 * access using the head B addresses can have strange results, ergo we leave
76 * tied mode in init once we know to what cr44 should be restored on exit
77 *
78 * the owner parameter is slightly abused:
79 * 0 and 1 are treated as head values and so the set value is (owner * 3)
80 * other values are treated as literal values to set
81 */
82void
83NVSetOwner(struct drm_device *dev, int owner)
84{
85 struct drm_nouveau_private *dev_priv = dev->dev_private;
86
87 if (owner == 1)
88 owner *= 3;
89
90 if (dev_priv->chipset == 0x11) {
91 /* This might seem stupid, but the blob does it and
92 * omitting it often locks the system up.
93 */
94 NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
95 NVReadVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX);
96 }
97
98 /* CR44 is always changed on CRTC0 */
99 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_44, owner);
100
101 if (dev_priv->chipset == 0x11) { /* set me harder */
102 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
103 NVWriteVgaCrtc(dev, 0, NV_CIO_CRE_2E, owner);
104 }
105}
106
107void
108NVBlankScreen(struct drm_device *dev, int head, bool blank)
109{
110 unsigned char seq1;
111
112 if (nv_two_heads(dev))
113 NVSetOwner(dev, head);
114
115 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
116
117 NVVgaSeqReset(dev, head, true);
118 if (blank)
119 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
120 else
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
122 NVVgaSeqReset(dev, head, false);
123}
124
125/*
126 * PLL setting
127 */
128
129static int
130powerctrl_1_shift(int chip_version, int reg)
131{
132 int shift = -4;
133
134 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
135 return shift;
136
137 switch (reg) {
138 case NV_RAMDAC_VPLL2:
139 shift += 4;
140 case NV_PRAMDAC_VPLL_COEFF:
141 shift += 4;
142 case NV_PRAMDAC_MPLL_COEFF:
143 shift += 4;
144 case NV_PRAMDAC_NVPLL_COEFF:
145 shift += 4;
146 }
147
148 /*
149 * the shift for vpll regs is only used for nv3x chips with a single
150 * stage pll
151 */
152 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
153 chip_version == 0x36 || chip_version >= 0x40))
154 shift = -4;
155
156 return shift;
157}
158
159static void
160setPLL_single(struct drm_device *dev, uint32_t reg, struct nouveau_pll_vals *pv)
161{
162 struct drm_nouveau_private *dev_priv = dev->dev_private;
163 int chip_version = dev_priv->vbios->chip_version;
164 uint32_t oldpll = NVReadRAMDAC(dev, 0, reg);
165 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
166 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
167 uint32_t saved_powerctrl_1 = 0;
168 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
169
170 if (oldpll == pll)
171 return; /* already set */
172
173 if (shift_powerctrl_1 >= 0) {
174 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
175 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
176 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
177 1 << shift_powerctrl_1);
178 }
179
180 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
181 /* upclock -- write new post divider first */
182 NVWriteRAMDAC(dev, 0, reg, pv->log2P << 16 | (oldpll & 0xffff));
183 else
184 /* downclock -- write new NM first */
185 NVWriteRAMDAC(dev, 0, reg, (oldpll & 0xffff0000) | pv->NM1);
186
187 if (chip_version < 0x17 && chip_version != 0x11)
188 /* wait a bit on older chips */
189 msleep(64);
190 NVReadRAMDAC(dev, 0, reg);
191
192 /* then write the other half as well */
193 NVWriteRAMDAC(dev, 0, reg, pll);
194
195 if (shift_powerctrl_1 >= 0)
196 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
197}
198
199static uint32_t
200new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
201{
202 bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
203
204 if (ss) /* single stage pll mode */
205 ramdac580 |= head_a ? NV_RAMDAC_580_VPLL1_ACTIVE :
206 NV_RAMDAC_580_VPLL2_ACTIVE;
207 else
208 ramdac580 &= head_a ? ~NV_RAMDAC_580_VPLL1_ACTIVE :
209 ~NV_RAMDAC_580_VPLL2_ACTIVE;
210
211 return ramdac580;
212}
213
214static void
215setPLL_double_highregs(struct drm_device *dev, uint32_t reg1,
216 struct nouveau_pll_vals *pv)
217{
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 int chip_version = dev_priv->vbios->chip_version;
220 bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
221 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
222 uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1);
223 uint32_t oldpll2 = !nv3035 ? NVReadRAMDAC(dev, 0, reg2) : 0;
224 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
225 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
226 uint32_t oldramdac580 = 0, ramdac580 = 0;
227 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
228 uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
229 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
230
231 /* model specific additions to generic pll1 and pll2 set up above */
232 if (nv3035) {
233 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
234 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
235 pll2 = 0;
236 }
237 if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
238 oldramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
239 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
240 if (oldramdac580 != ramdac580)
241 oldpll1 = ~0; /* force mismatch */
242 if (single_stage)
243 /* magic value used by nvidia in single stage mode */
244 pll2 |= 0x011f;
245 }
246 if (chip_version > 0x70)
247 /* magic bits set by the blob (but not the bios) on g71-73 */
248 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
249
250 if (oldpll1 == pll1 && oldpll2 == pll2)
251 return; /* already set */
252
253 if (shift_powerctrl_1 >= 0) {
254 saved_powerctrl_1 = nvReadMC(dev, NV_PBUS_POWERCTRL_1);
255 nvWriteMC(dev, NV_PBUS_POWERCTRL_1,
256 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
257 1 << shift_powerctrl_1);
258 }
259
260 if (chip_version >= 0x40) {
261 int shift_c040 = 14;
262
263 switch (reg1) {
264 case NV_PRAMDAC_MPLL_COEFF:
265 shift_c040 += 2;
266 case NV_PRAMDAC_NVPLL_COEFF:
267 shift_c040 += 2;
268 case NV_RAMDAC_VPLL2:
269 shift_c040 += 2;
270 case NV_PRAMDAC_VPLL_COEFF:
271 shift_c040 += 2;
272 }
273
274 savedc040 = nvReadMC(dev, 0xc040);
275 if (shift_c040 != 14)
276 nvWriteMC(dev, 0xc040, savedc040 & ~(3 << shift_c040));
277 }
278
279 if (oldramdac580 != ramdac580)
280 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_580, ramdac580);
281
282 if (!nv3035)
283 NVWriteRAMDAC(dev, 0, reg2, pll2);
284 NVWriteRAMDAC(dev, 0, reg1, pll1);
285
286 if (shift_powerctrl_1 >= 0)
287 nvWriteMC(dev, NV_PBUS_POWERCTRL_1, saved_powerctrl_1);
288 if (chip_version >= 0x40)
289 nvWriteMC(dev, 0xc040, savedc040);
290}
291
292static void
293setPLL_double_lowregs(struct drm_device *dev, uint32_t NMNMreg,
294 struct nouveau_pll_vals *pv)
295{
296 /* When setting PLLs, there is a merry game of disabling and enabling
297 * various bits of hardware during the process. This function is a
298 * synthesis of six nv4x traces, nearly each card doing a subtly
299 * different thing. With luck all the necessary bits for each card are
300 * combined herein. Without luck it deviates from each card's formula
301 * so as to not work on any :)
302 */
303
304 uint32_t Preg = NMNMreg - 4;
305 bool mpll = Preg == 0x4020;
306 uint32_t oldPval = nvReadMC(dev, Preg);
307 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
308 uint32_t Pval = (oldPval & (mpll ? ~(0x11 << 16) : ~(1 << 16))) |
309 0xc << 28 | pv->log2P << 16;
310 uint32_t saved4600 = 0;
311 /* some cards have different maskc040s */
312 uint32_t maskc040 = ~(3 << 14), savedc040;
313 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
314
315 if (nvReadMC(dev, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
316 return;
317
318 if (Preg == 0x4000)
319 maskc040 = ~0x333;
320 if (Preg == 0x4058)
321 maskc040 = ~(0xc << 24);
322
323 if (mpll) {
324 struct pll_lims pll_lim;
325 uint8_t Pval2;
326
327 if (get_pll_limits(dev, Preg, &pll_lim))
328 return;
329
330 Pval2 = pv->log2P + pll_lim.log2p_bias;
331 if (Pval2 > pll_lim.max_log2p)
332 Pval2 = pll_lim.max_log2p;
333 Pval |= 1 << 28 | Pval2 << 20;
334
335 saved4600 = nvReadMC(dev, 0x4600);
336 nvWriteMC(dev, 0x4600, saved4600 | 8 << 28);
337 }
338 if (single_stage)
339 Pval |= mpll ? 1 << 12 : 1 << 8;
340
341 nvWriteMC(dev, Preg, oldPval | 1 << 28);
342 nvWriteMC(dev, Preg, Pval & ~(4 << 28));
343 if (mpll) {
344 Pval |= 8 << 20;
345 nvWriteMC(dev, 0x4020, Pval & ~(0xc << 28));
346 nvWriteMC(dev, 0x4038, Pval & ~(0xc << 28));
347 }
348
349 savedc040 = nvReadMC(dev, 0xc040);
350 nvWriteMC(dev, 0xc040, savedc040 & maskc040);
351
352 nvWriteMC(dev, NMNMreg, NMNM);
353 if (NMNMreg == 0x4024)
354 nvWriteMC(dev, 0x403c, NMNM);
355
356 nvWriteMC(dev, Preg, Pval);
357 if (mpll) {
358 Pval &= ~(8 << 20);
359 nvWriteMC(dev, 0x4020, Pval);
360 nvWriteMC(dev, 0x4038, Pval);
361 nvWriteMC(dev, 0x4600, saved4600);
362 }
363
364 nvWriteMC(dev, 0xc040, savedc040);
365
366 if (mpll) {
367 nvWriteMC(dev, 0x4020, Pval & ~(1 << 28));
368 nvWriteMC(dev, 0x4038, Pval & ~(1 << 28));
369 }
370}
371
372void
373nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1,
374 struct nouveau_pll_vals *pv)
375{
376 struct drm_nouveau_private *dev_priv = dev->dev_private;
377 int cv = dev_priv->vbios->chip_version;
378
379 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
380 cv >= 0x40) {
381 if (reg1 > 0x405c)
382 setPLL_double_highregs(dev, reg1, pv);
383 else
384 setPLL_double_lowregs(dev, reg1, pv);
385 } else
386 setPLL_single(dev, reg1, pv);
387}
388
389/*
390 * PLL getting
391 */
392
393static void
394nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1,
395 uint32_t pll2, struct nouveau_pll_vals *pllvals)
396{
397 struct drm_nouveau_private *dev_priv = dev->dev_private;
398
399 /* to force parsing as single stage (i.e. nv40 vplls) pass pll2 as 0 */
400
401 /* log2P is & 0x7 as never more than 7, and nv30/35 only uses 3 bits */
402 pllvals->log2P = (pll1 >> 16) & 0x7;
403 pllvals->N2 = pllvals->M2 = 1;
404
405 if (reg1 <= 0x405c) {
406 pllvals->NM1 = pll2 & 0xffff;
407 /* single stage NVPLL and VPLLs use 1 << 8, MPLL uses 1 << 12 */
408 if (!(pll1 & 0x1100))
409 pllvals->NM2 = pll2 >> 16;
410 } else {
411 pllvals->NM1 = pll1 & 0xffff;
412 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2)
413 pllvals->NM2 = pll2 & 0xffff;
414 else if (dev_priv->chipset == 0x30 || dev_priv->chipset == 0x35) {
415 pllvals->M1 &= 0xf; /* only 4 bits */
416 if (pll1 & NV30_RAMDAC_ENABLE_VCO2) {
417 pllvals->M2 = (pll1 >> 4) & 0x7;
418 pllvals->N2 = ((pll1 >> 21) & 0x18) |
419 ((pll1 >> 19) & 0x7);
420 }
421 }
422 }
423}
424
425int
426nouveau_hw_get_pllvals(struct drm_device *dev, enum pll_types plltype,
427 struct nouveau_pll_vals *pllvals)
428{
429 struct drm_nouveau_private *dev_priv = dev->dev_private;
430 const uint32_t nv04_regs[MAX_PLL_TYPES] = { NV_PRAMDAC_NVPLL_COEFF,
431 NV_PRAMDAC_MPLL_COEFF,
432 NV_PRAMDAC_VPLL_COEFF,
433 NV_RAMDAC_VPLL2 };
434 const uint32_t nv40_regs[MAX_PLL_TYPES] = { 0x4000,
435 0x4020,
436 NV_PRAMDAC_VPLL_COEFF,
437 NV_RAMDAC_VPLL2 };
438 uint32_t reg1, pll1, pll2 = 0;
439 struct pll_lims pll_lim;
440 int ret;
441
442 if (dev_priv->card_type < NV_40)
443 reg1 = nv04_regs[plltype];
444 else
445 reg1 = nv40_regs[plltype];
446
447 pll1 = nvReadMC(dev, reg1);
448
449 if (reg1 <= 0x405c)
450 pll2 = nvReadMC(dev, reg1 + 4);
451 else if (nv_two_reg_pll(dev)) {
452 uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70);
453
454 pll2 = nvReadMC(dev, reg2);
455 }
456
457 if (dev_priv->card_type == 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) {
458 uint32_t ramdac580 = NVReadRAMDAC(dev, 0, NV_PRAMDAC_580);
459
460 /* check whether vpll has been forced into single stage mode */
461 if (reg1 == NV_PRAMDAC_VPLL_COEFF) {
462 if (ramdac580 & NV_RAMDAC_580_VPLL1_ACTIVE)
463 pll2 = 0;
464 } else
465 if (ramdac580 & NV_RAMDAC_580_VPLL2_ACTIVE)
466 pll2 = 0;
467 }
468
469 nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals);
470
471 ret = get_pll_limits(dev, plltype, &pll_lim);
472 if (ret)
473 return ret;
474
475 pllvals->refclk = pll_lim.refclk;
476
477 return 0;
478}
479
480int
481nouveau_hw_pllvals_to_clk(struct nouveau_pll_vals *pv)
482{
483 /* Avoid divide by zero if called at an inappropriate time */
484 if (!pv->M1 || !pv->M2)
485 return 0;
486
487 return pv->N1 * pv->N2 * pv->refclk / (pv->M1 * pv->M2) >> pv->log2P;
488}
489
490int
491nouveau_hw_get_clock(struct drm_device *dev, enum pll_types plltype)
492{
493 struct nouveau_pll_vals pllvals;
494
495 if (plltype == MPLL && (dev->pci_device & 0x0ff0) == CHIPSET_NFORCE) {
496 uint32_t mpllP;
497
498 pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
499 if (!mpllP)
500 mpllP = 4;
501
502 return 400000 / mpllP;
503 } else
504 if (plltype == MPLL && (dev->pci_device & 0xff0) == CHIPSET_NFORCE2) {
505 uint32_t clock;
506
507 pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
508 return clock;
509 }
510
511 nouveau_hw_get_pllvals(dev, plltype, &pllvals);
512
513 return nouveau_hw_pllvals_to_clk(&pllvals);
514}
515
516static void
517nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
518{
519 /* the vpll on an unused head can come up with a random value, way
520 * beyond the pll limits. for some reason this causes the chip to
521 * lock up when reading the dac palette regs, so set a valid pll here
522 * when such a condition detected. only seen on nv11 to date
523 */
524
525 struct pll_lims pll_lim;
526 struct nouveau_pll_vals pv;
527 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
528
529 if (get_pll_limits(dev, head ? VPLL2 : VPLL1, &pll_lim))
530 return;
531 nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &pv);
532
533 if (pv.M1 >= pll_lim.vco1.min_m && pv.M1 <= pll_lim.vco1.max_m &&
534 pv.N1 >= pll_lim.vco1.min_n && pv.N1 <= pll_lim.vco1.max_n &&
535 pv.log2P <= pll_lim.max_log2p)
536 return;
537
538 NV_WARN(dev, "VPLL %d outwith limits, attempting to fix\n", head + 1);
539
540 /* set lowest clock within static limits */
541 pv.M1 = pll_lim.vco1.max_m;
542 pv.N1 = pll_lim.vco1.min_n;
543 pv.log2P = pll_lim.max_usable_log2p;
544 nouveau_hw_setpll(dev, pllreg, &pv);
545}
546
547/*
548 * vga font save/restore
549 */
550
551static void nouveau_vga_font_io(struct drm_device *dev,
552 void __iomem *iovram,
553 bool save, unsigned plane)
554{
555 struct drm_nouveau_private *dev_priv = dev->dev_private;
556 unsigned i;
557
558 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, 1 << plane);
559 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, plane);
560 for (i = 0; i < 16384; i++) {
561 if (save) {
562 dev_priv->saved_vga_font[plane][i] =
563 ioread32_native(iovram + i * 4);
564 } else {
565 iowrite32_native(dev_priv->saved_vga_font[plane][i],
566 iovram + i * 4);
567 }
568 }
569}
570
571void
572nouveau_hw_save_vga_fonts(struct drm_device *dev, bool save)
573{
574 uint8_t misc, gr4, gr5, gr6, seq2, seq4;
575 bool graphicsmode;
576 unsigned plane;
577 void __iomem *iovram;
578
579 if (nv_two_heads(dev))
580 NVSetOwner(dev, 0);
581
582 NVSetEnablePalette(dev, 0, true);
583 graphicsmode = NVReadVgaAttr(dev, 0, NV_CIO_AR_MODE_INDEX) & 1;
584 NVSetEnablePalette(dev, 0, false);
585
586 if (graphicsmode) /* graphics mode => framebuffer => no need to save */
587 return;
588
589 NV_INFO(dev, "%sing VGA fonts\n", save ? "Sav" : "Restor");
590
591 /* map first 64KiB of VRAM, holds VGA fonts etc */
592 iovram = ioremap(pci_resource_start(dev->pdev, 1), 65536);
593 if (!iovram) {
594 NV_ERROR(dev, "Failed to map VRAM, "
595 "cannot save/restore VGA fonts.\n");
596 return;
597 }
598
599 if (nv_two_heads(dev))
600 NVBlankScreen(dev, 1, true);
601 NVBlankScreen(dev, 0, true);
602
603 /* save control regs */
604 misc = NVReadPRMVIO(dev, 0, NV_PRMVIO_MISC__READ);
605 seq2 = NVReadVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX);
606 seq4 = NVReadVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX);
607 gr4 = NVReadVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX);
608 gr5 = NVReadVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX);
609 gr6 = NVReadVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX);
610
611 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, 0x67);
612 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, 0x6);
613 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, 0x0);
614 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, 0x5);
615
616 /* store font in planes 0..3 */
617 for (plane = 0; plane < 4; plane++)
618 nouveau_vga_font_io(dev, iovram, save, plane);
619
620 /* restore control regs */
621 NVWritePRMVIO(dev, 0, NV_PRMVIO_MISC__WRITE, misc);
622 NVWriteVgaGr(dev, 0, NV_VIO_GX_READ_MAP_INDEX, gr4);
623 NVWriteVgaGr(dev, 0, NV_VIO_GX_MODE_INDEX, gr5);
624 NVWriteVgaGr(dev, 0, NV_VIO_GX_MISC_INDEX, gr6);
625 NVWriteVgaSeq(dev, 0, NV_VIO_SR_PLANE_MASK_INDEX, seq2);
626 NVWriteVgaSeq(dev, 0, NV_VIO_SR_MEM_MODE_INDEX, seq4);
627
628 if (nv_two_heads(dev))
629 NVBlankScreen(dev, 1, false);
630 NVBlankScreen(dev, 0, false);
631
632 iounmap(iovram);
633}
634
635/*
636 * mode state save/load
637 */
638
639static void
640rd_cio_state(struct drm_device *dev, int head,
641 struct nv04_crtc_reg *crtcstate, int index)
642{
643 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
644}
645
646static void
647wr_cio_state(struct drm_device *dev, int head,
648 struct nv04_crtc_reg *crtcstate, int index)
649{
650 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
651}
652
653static void
654nv_save_state_ramdac(struct drm_device *dev, int head,
655 struct nv04_mode_state *state)
656{
657 struct drm_nouveau_private *dev_priv = dev->dev_private;
658 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
659 int i;
660
661 if (dev_priv->card_type >= NV_10)
662 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
663
664 nouveau_hw_get_pllvals(dev, head ? VPLL2 : VPLL1, &regp->pllvals);
665 state->pllsel = NVReadRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT);
666 if (nv_two_heads(dev))
667 state->sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK);
668 if (dev_priv->chipset == 0x11)
669 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
670
671 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
672
673 if (nv_gf4_disp_arch(dev))
674 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
675 if (dev_priv->chipset >= 0x30)
676 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
677
678 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
679 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
680 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
681 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
682 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
683 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
684 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
685 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
686
687 for (i = 0; i < 7; i++) {
688 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
689 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
690 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
691 }
692
693 if (nv_gf4_disp_arch(dev)) {
694 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
695 for (i = 0; i < 3; i++) {
696 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
697 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
698 }
699 }
700
701 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
702 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
703 if (!nv_gf4_disp_arch(dev) && head == 0) {
704 /* early chips don't allow access to PRAMDAC_TMDS_* without
705 * the head A FPCLK on (nv11 even locks up) */
706 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0 &
707 ~NV_PRAMDAC_FP_DEBUG_0_PWRDOWN_FPCLK);
708 }
709 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
710 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
711
712 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
713
714 if (nv_gf4_disp_arch(dev))
715 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
716
717 if (dev_priv->card_type == NV_40) {
718 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
719 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
720 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
721
722 for (i = 0; i < 38; i++)
723 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
724 NV_PRAMDAC_CTV + 4*i);
725 }
726}
727
728static void
729nv_load_state_ramdac(struct drm_device *dev, int head,
730 struct nv04_mode_state *state)
731{
732 struct drm_nouveau_private *dev_priv = dev->dev_private;
733 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
734 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
735 int i;
736
737 if (dev_priv->card_type >= NV_10)
738 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
739
740 nouveau_hw_setpll(dev, pllreg, &regp->pllvals);
741 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_PLL_COEFF_SELECT, state->pllsel);
742 if (nv_two_heads(dev))
743 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, state->sel_clk);
744 if (dev_priv->chipset == 0x11)
745 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
746
747 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
748
749 if (nv_gf4_disp_arch(dev))
750 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
751 if (dev_priv->chipset >= 0x30)
752 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
753
754 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
755 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
756 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
757 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
758 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
759 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
760 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
761 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
762
763 for (i = 0; i < 7; i++) {
764 uint32_t ramdac_reg = NV_PRAMDAC_FP_VDISPLAY_END + (i * 4);
765
766 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
767 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
768 }
769
770 if (nv_gf4_disp_arch(dev)) {
771 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
772 for (i = 0; i < 3; i++) {
773 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
774 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
775 }
776 }
777
778 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
779 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
780 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
781 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
782
783 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
784
785 if (nv_gf4_disp_arch(dev))
786 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
787
788 if (dev_priv->card_type == NV_40) {
789 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
790 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
791 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
792
793 for (i = 0; i < 38; i++)
794 NVWriteRAMDAC(dev, head,
795 NV_PRAMDAC_CTV + 4*i, regp->ctv_regs[i]);
796 }
797}
798
799static void
800nv_save_state_vga(struct drm_device *dev, int head,
801 struct nv04_mode_state *state)
802{
803 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
804 int i;
805
806 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
807
808 for (i = 0; i < 25; i++)
809 rd_cio_state(dev, head, regp, i);
810
811 NVSetEnablePalette(dev, head, true);
812 for (i = 0; i < 21; i++)
813 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
814 NVSetEnablePalette(dev, head, false);
815
816 for (i = 0; i < 9; i++)
817 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
818
819 for (i = 0; i < 5; i++)
820 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
821}
822
823static void
824nv_load_state_vga(struct drm_device *dev, int head,
825 struct nv04_mode_state *state)
826{
827 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
828 int i;
829
830 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
831
832 for (i = 0; i < 5; i++)
833 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
834
835 nv_lock_vga_crtc_base(dev, head, false);
836 for (i = 0; i < 25; i++)
837 wr_cio_state(dev, head, regp, i);
838 nv_lock_vga_crtc_base(dev, head, true);
839
840 for (i = 0; i < 9; i++)
841 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
842
843 NVSetEnablePalette(dev, head, true);
844 for (i = 0; i < 21; i++)
845 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
846 NVSetEnablePalette(dev, head, false);
847}
848
849static void
850nv_save_state_ext(struct drm_device *dev, int head,
851 struct nv04_mode_state *state)
852{
853 struct drm_nouveau_private *dev_priv = dev->dev_private;
854 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
855 int i;
856
857 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
858 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
859 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
860 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
861 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
862 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
863 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
864
865 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
866 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
867 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
868 if (dev_priv->card_type >= NV_30)
869 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
870 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
871 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
872 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
873 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
874 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
875
876 if (dev_priv->card_type >= NV_10) {
877 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
878 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
879
880 if (dev_priv->card_type >= NV_30)
881 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
882
883 if (dev_priv->card_type == NV_40)
884 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
885
886 if (nv_two_heads(dev))
887 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
888 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
889 }
890
891 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
892
893 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
894 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
895 if (dev_priv->card_type >= NV_10) {
896 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
897 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
898 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
899 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
900 }
901 /* NV11 and NV20 don't have this, they stop at 0x52. */
902 if (nv_gf4_disp_arch(dev)) {
903 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
904 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
905
906 for (i = 0; i < 0x10; i++)
907 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
908 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
909 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
910
911 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
912 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
913 }
914
915 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
916}
917
918static void
919nv_load_state_ext(struct drm_device *dev, int head,
920 struct nv04_mode_state *state)
921{
922 struct drm_nouveau_private *dev_priv = dev->dev_private;
923 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
924 uint32_t reg900;
925 int i;
926
927 if (dev_priv->card_type >= NV_10) {
928 if (nv_two_heads(dev))
929 /* setting ENGINE_CTRL (EC) *must* come before
930 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
931 * EC that should not be overwritten by writing stale EC
932 */
933 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
934
935 nvWriteVIDEO(dev, NV_PVIDEO_STOP, 1);
936 nvWriteVIDEO(dev, NV_PVIDEO_INTR_EN, 0);
937 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(0), 0);
938 nvWriteVIDEO(dev, NV_PVIDEO_OFFSET_BUFF(1), 0);
939 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(0), dev_priv->fb_available_size - 1);
940 nvWriteVIDEO(dev, NV_PVIDEO_LIMIT(1), dev_priv->fb_available_size - 1);
941 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(0), dev_priv->fb_available_size - 1);
942 nvWriteVIDEO(dev, NV_PVIDEO_UVPLANE_LIMIT(1), dev_priv->fb_available_size - 1);
943 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
944
945 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
946 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
947 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
948
949 if (dev_priv->card_type >= NV_30)
950 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
951
952 if (dev_priv->card_type == NV_40) {
953 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
954
955 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
956 if (regp->crtc_cfg == NV_PCRTC_CONFIG_START_ADDRESS_HSYNC)
957 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
958 else
959 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
960 }
961 }
962
963 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
964
965 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
966 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
967 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
968 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
969 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
970 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
971 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
972 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
973 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
974 if (dev_priv->card_type >= NV_30)
975 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
976
977 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
978 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
979 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
980 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
981 if (dev_priv->card_type == NV_40)
982 nv_fix_nv40_hw_cursor(dev, head);
983 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
984
985 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
986 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
987 if (dev_priv->card_type >= NV_10) {
988 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
989 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
990 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
991 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
992 }
993 /* NV11 and NV20 stop at 0x52. */
994 if (nv_gf4_disp_arch(dev)) {
995 if (dev_priv->card_type == NV_10) {
996 /* Not waiting for vertical retrace before modifying
997 CRE_53/CRE_54 causes lockups. */
998 nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8);
999 nouveau_wait_until(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
1000 }
1001
1002 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
1003 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
1004
1005 for (i = 0; i < 0x10; i++)
1006 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
1007 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
1008 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
1009
1010 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
1011 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
1012 }
1013
1014 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
1015
1016 /* Setting 1 on this value gives you interrupts for every vblank period. */
1017 NVWriteCRTC(dev, head, NV_PCRTC_INTR_EN_0, 0);
1018 NVWriteCRTC(dev, head, NV_PCRTC_INTR_0, NV_PCRTC_INTR_0_VBLANK);
1019}
1020
1021static void
1022nv_save_state_palette(struct drm_device *dev, int head,
1023 struct nv04_mode_state *state)
1024{
1025 int head_offset = head * NV_PRMDIO_SIZE, i;
1026
1027 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1028 NV_PRMDIO_PIXEL_MASK_MASK);
1029 nv_wr08(dev, NV_PRMDIO_READ_MODE_ADDRESS + head_offset, 0x0);
1030
1031 for (i = 0; i < 768; i++) {
1032 state->crtc_reg[head].DAC[i] = nv_rd08(dev,
1033 NV_PRMDIO_PALETTE_DATA + head_offset);
1034 }
1035
1036 NVSetEnablePalette(dev, head, false);
1037}
1038
1039void
1040nouveau_hw_load_state_palette(struct drm_device *dev, int head,
1041 struct nv04_mode_state *state)
1042{
1043 int head_offset = head * NV_PRMDIO_SIZE, i;
1044
1045 nv_wr08(dev, NV_PRMDIO_PIXEL_MASK + head_offset,
1046 NV_PRMDIO_PIXEL_MASK_MASK);
1047 nv_wr08(dev, NV_PRMDIO_WRITE_MODE_ADDRESS + head_offset, 0x0);
1048
1049 for (i = 0; i < 768; i++) {
1050 nv_wr08(dev, NV_PRMDIO_PALETTE_DATA + head_offset,
1051 state->crtc_reg[head].DAC[i]);
1052 }
1053
1054 NVSetEnablePalette(dev, head, false);
1055}
1056
1057void nouveau_hw_save_state(struct drm_device *dev, int head,
1058 struct nv04_mode_state *state)
1059{
1060 struct drm_nouveau_private *dev_priv = dev->dev_private;
1061
1062 if (dev_priv->chipset == 0x11)
1063 /* NB: no attempt is made to restore the bad pll later on */
1064 nouveau_hw_fix_bad_vpll(dev, head);
1065 nv_save_state_ramdac(dev, head, state);
1066 nv_save_state_vga(dev, head, state);
1067 nv_save_state_palette(dev, head, state);
1068 nv_save_state_ext(dev, head, state);
1069}
1070
1071void nouveau_hw_load_state(struct drm_device *dev, int head,
1072 struct nv04_mode_state *state)
1073{
1074 NVVgaProtect(dev, head, true);
1075 nv_load_state_ramdac(dev, head, state);
1076 nv_load_state_ext(dev, head, state);
1077 nouveau_hw_load_state_palette(dev, head, state);
1078 nv_load_state_vga(dev, head, state);
1079 NVVgaProtect(dev, head, false);
1080}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 05:56:05 -0500