Merge tag 'v3.16-rc6' into MTD development branch

Linux 3.16-rc6

23 files changed, 337 insertions, 95 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 601caa88c092..b8c689202c40 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -446,7 +446,9 @@ static int i915_gem_object_info(struct seq_file *m, void* data)
 
                 memset(&stats, 0, sizeof(stats));
                 stats.file_priv = file->driver_priv;
+                spin_lock(&file->table_lock);
                 idr_for_each(&file->object_idr, per_file_stats, &stats);
+                spin_unlock(&file->table_lock);
                 /*
                  * Although we have a valid reference on file->pid, that does
                  * not guarantee that the task_struct who called get_pid() is
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 4c22a5b7f4c5..d44344140627 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -36,6 +36,8 @@
 #include "i915_drv.h"
 #include "i915_trace.h"
 #include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/vt.h>
 #include <linux/vgaarb.h>
 #include <linux/acpi.h>
 #include <linux/pnp.h>
@@ -1386,7 +1388,6 @@ cleanup_gem:
         i915_gem_context_fini(dev);
         mutex_unlock(&dev->struct_mutex);
         WARN_ON(dev_priv->mm.aliasing_ppgtt);
-        drm_mm_takedown(&dev_priv->gtt.base.mm);
 cleanup_irq:
         drm_irq_uninstall(dev);
 cleanup_gem_stolen:
@@ -1450,6 +1451,39 @@ static void i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 }
 #endif
 
+#if !defined(CONFIG_VGA_CONSOLE)
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        return 0;
+}
+#elif !defined(CONFIG_DUMMY_CONSOLE)
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        return -ENODEV;
+}
+#else
+static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
+{
+        int ret = 0;
+
+        DRM_INFO("Replacing VGA console driver\n");
+
+        console_lock();
+        if (con_is_bound(&vga_con))
+                ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
+        if (ret == 0) {
+                ret = do_unregister_con_driver(&vga_con);
+
+                /* Ignore "already unregistered". */
+                if (ret == -ENODEV)
+                        ret = 0;
+        }
+        console_unlock();
+
+        return ret;
+}
+#endif
+
 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 {
         const struct intel_device_info *info = &dev_priv->info;
@@ -1623,8 +1657,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         if (ret)
                 goto out_regs;
 
-        if (drm_core_check_feature(dev, DRIVER_MODESET))
+        if (drm_core_check_feature(dev, DRIVER_MODESET)) {
+                ret = i915_kick_out_vgacon(dev_priv);
+                if (ret) {
+                        DRM_ERROR("failed to remove conflicting VGA console\n");
+                        goto out_gtt;
+                }
+
                 i915_kick_out_firmware_fb(dev_priv);
+        }
 
         pci_set_master(dev->pdev);
 
@@ -1756,8 +1797,6 @@ out_mtrrfree:
         arch_phys_wc_del(dev_priv->gtt.mtrr);
         io_mapping_free(dev_priv->gtt.mappable);
 out_gtt:
-        list_del(&dev_priv->gtt.base.global_link);
-        drm_mm_takedown(&dev_priv->gtt.base.mm);
         dev_priv->gtt.base.cleanup(&dev_priv->gtt.base);
 out_regs:
         intel_uncore_fini(dev);
@@ -1846,7 +1885,6 @@ int i915_driver_unload(struct drm_device *dev)
                         i915_free_hws(dev);
         }
 
-        list_del(&dev_priv->gtt.base.global_link);
         WARN_ON(!list_empty(&dev_priv->vm_list));
 
         drm_vblank_cleanup(dev);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 49414d30e8d4..374f964323ad 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -656,6 +656,7 @@ enum intel_sbi_destination {
 #define QUIRK_PIPEA_FORCE (1<<0)
 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
+#define QUIRK_BACKLIGHT_PRESENT (1<<3)
 
 struct intel_fbdev;
 struct intel_fbc_work;
@@ -977,6 +978,8 @@ struct i915_power_well {
         bool always_on;
         /* power well enable/disable usage count */
         int count;
+        /* cached hw enabled state */
+        bool hw_enabled;
         unsigned long domains;
         unsigned long data;
         const struct i915_power_well_ops *ops;
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 3ffe308d5893..a5ddf3bce9c3 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -598,6 +598,7 @@ static int do_switch(struct intel_engine_cs *ring,
         struct intel_context *from = ring->last_context;
         struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(to);
         u32 hw_flags = 0;
+        bool uninitialized = false;
         int ret, i;
 
         if (from != NULL && ring == &dev_priv->ring[RCS]) {
@@ -696,19 +697,20 @@ static int do_switch(struct intel_engine_cs *ring,
                 i915_gem_context_unreference(from);
         }
 
+        uninitialized = !to->is_initialized && from == NULL;
+        to->is_initialized = true;
+
 done:
         i915_gem_context_reference(to);
         ring->last_context = to;
         to->last_ring = ring;
 
-        if (ring->id == RCS && !to->is_initialized && from == NULL) {
+        if (uninitialized) {
                 ret = i915_gem_render_state_init(ring);
                 if (ret)
                         DRM_ERROR("init render state: %d\n", ret);
         }
 
-        to->is_initialized = true;
-
         return 0;
 
 unpin_out:
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index eec820aec022..8b3cde703364 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1992,7 +1992,10 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
 
         struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
 
-        drm_mm_takedown(&vm->mm);
+        if (drm_mm_initialized(&vm->mm)) {
+                drm_mm_takedown(&vm->mm);
+                list_del(&vm->global_link);
+        }
         iounmap(gtt->gsm);
         teardown_scratch_page(vm->dev);
 }
@@ -2025,6 +2028,10 @@ static int i915_gmch_probe(struct drm_device *dev,
 
 static void i915_gmch_remove(struct i915_address_space *vm)
 {
+        if (drm_mm_initialized(&vm->mm)) {
+                drm_mm_takedown(&vm->mm);
+                list_del(&vm->global_link);
+        }
         intel_gmch_remove();
 }
 
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index 62ef55ba061c..7465ab0fd396 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -74,6 +74,50 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
         if (base == 0)
                 return 0;
 
+        /* make sure we don't clobber the GTT if it's within stolen memory */
+        if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
+                struct {
+                        u32 start, end;
+                } stolen[2] = {
+                        { .start = base, .end = base + dev_priv->gtt.stolen_size, },
+                        { .start = base, .end = base + dev_priv->gtt.stolen_size, },
+                };
+                u64 gtt_start, gtt_end;
+
+                gtt_start = I915_READ(PGTBL_CTL);
+                if (IS_GEN4(dev))
+                        gtt_start = (gtt_start & PGTBL_ADDRESS_LO_MASK) |
+                                (gtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
+                else
+                        gtt_start &= PGTBL_ADDRESS_LO_MASK;
+                gtt_end = gtt_start + gtt_total_entries(dev_priv->gtt) * 4;
+
+                if (gtt_start >= stolen[0].start && gtt_start < stolen[0].end)
+                        stolen[0].end = gtt_start;
+                if (gtt_end > stolen[1].start && gtt_end <= stolen[1].end)
+                        stolen[1].start = gtt_end;
+
+                /* pick the larger of the two chunks */
+                if (stolen[0].end - stolen[0].start >
+                    stolen[1].end - stolen[1].start) {
+                        base = stolen[0].start;
+                        dev_priv->gtt.stolen_size = stolen[0].end - stolen[0].start;
+                } else {
+                        base = stolen[1].start;
+                        dev_priv->gtt.stolen_size = stolen[1].end - stolen[1].start;
+                }
+
+                if (stolen[0].start != stolen[1].start ||
+                    stolen[0].end != stolen[1].end) {
+                        DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
+                                      (unsigned long long) gtt_start,
+                                      (unsigned long long) gtt_end - 1);
+                        DRM_DEBUG_KMS("Stolen memory adjusted to 0x%x-0x%x\n",
+                                      base, base + (u32) dev_priv->gtt.stolen_size - 1);
+                }
+        }
+
+
         /* Verify that nothing else uses this physical address. Stolen
          * memory should be reserved by the BIOS and hidden from the
          * kernel. So if the region is already marked as busy, something
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 87ec60e181a7..66cf41765bf9 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -888,6 +888,8 @@ static void i915_gem_record_rings(struct drm_device *dev,
         for (i = 0; i < I915_NUM_RINGS; i++) {
                 struct intel_engine_cs *ring = &dev_priv->ring[i];
 
+                error->ring[i].pid = -1;
+
                 if (ring->dev == NULL)
                         continue;
 
@@ -895,7 +897,6 @@ static void i915_gem_record_rings(struct drm_device *dev,
 
                 i915_record_ring_state(dev, ring, &error->ring[i]);
 
-                error->ring[i].pid = -1;
                 request = i915_gem_find_active_request(ring);
                 if (request) {
                         /* We need to copy these to an anonymous buffer
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6f8017a7e937..267f069765ad 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2847,10 +2847,14 @@ static int semaphore_passed(struct intel_engine_cs *ring)
         struct intel_engine_cs *signaller;
         u32 seqno, ctl;
 
-        ring->hangcheck.deadlock = true;
+        ring->hangcheck.deadlock++;
 
         signaller = semaphore_waits_for(ring, &seqno);
-        if (signaller == NULL || signaller->hangcheck.deadlock)
+        if (signaller == NULL)
+                return -1;
+
+        /* Prevent pathological recursion due to driver bugs */
+        if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
                 return -1;
 
         /* cursory check for an unkickable deadlock */
@@ -2858,7 +2862,13 @@ static int semaphore_passed(struct intel_engine_cs *ring)
         if (ctl & RING_WAIT_SEMAPHORE && semaphore_passed(signaller) < 0)
                 return -1;
 
-        return i915_seqno_passed(signaller->get_seqno(signaller, false), seqno);
+        if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
+                return 1;
+
+        if (signaller->hangcheck.deadlock)
+                return -1;
+
+        return 0;
 }
 
 static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
@@ -2867,7 +2877,7 @@ static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
         int i;
 
         for_each_ring(ring, dev_priv, i)
-                ring->hangcheck.deadlock = false;
+                ring->hangcheck.deadlock = 0;
 }
 
 static enum intel_ring_hangcheck_action
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e691b30b2817..a5bab61bfc00 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -942,6 +942,9 @@ enum punit_power_well {
 /*
  * Instruction and interrupt control regs
  */
+#define PGTBL_CTL       0x02020
+#define   PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
+#define   PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
 #define PGTBL_ER        0x02024
 #define RENDER_RING_BASE        0x02000
 #define BSD_RING_BASE           0x04000
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index 1ee98f121a00..827498e081df 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -315,9 +315,6 @@ parse_lfp_backlight(struct drm_i915_private *dev_priv, struct bdb_header *bdb)
         const struct bdb_lfp_backlight_data *backlight_data;
         const struct bdb_lfp_backlight_data_entry *entry;
 
-        /* Err to enabling backlight if no backlight block. */
-        dev_priv->vbt.backlight.present = true;
-
         backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT);
         if (!backlight_data)
                 return;
@@ -1088,6 +1085,9 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 
         dev_priv->vbt.crt_ddc_pin = GMBUS_PORT_VGADDC;
 
+        /* Default to having backlight */
+        dev_priv->vbt.backlight.present = true;
+
         /* LFP panel data */
         dev_priv->vbt.lvds_dither = 1;
         dev_priv->vbt.lvds_vbt = 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efd3cf50cb0f..f0be855ddf45 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2087,6 +2087,7 @@ void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
                                           enum plane plane, enum pipe pipe)
 {
+        struct drm_device *dev = dev_priv->dev;
         struct intel_crtc *intel_crtc =
                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
         int reg;
@@ -2106,6 +2107,14 @@ static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
 
         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
         intel_flush_primary_plane(dev_priv, plane);
+
+        /*
+         * BDW signals flip done immediately if the plane
+         * is disabled, even if the plane enable is already
+         * armed to occur at the next vblank :(
+         */
+        if (IS_BROADWELL(dev))
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
 }
 
 /**
@@ -4564,7 +4573,10 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
         if (intel_crtc->active)
                 return;
 
-        vlv_prepare_pll(intel_crtc);
+        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
+
+        if (!is_dsi && !IS_CHERRYVIEW(dev))
+                vlv_prepare_pll(intel_crtc);
 
         /* Set up the display plane register */
         dspcntr = DISPPLANE_GAMMA_ENABLE;
@@ -4598,8 +4610,6 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc)
                 if (encoder->pre_pll_enable)
                         encoder->pre_pll_enable(encoder);
 
-        is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
-
         if (!is_dsi) {
                 if (IS_CHERRYVIEW(dev))
                         chv_enable_pll(intel_crtc);
@@ -11087,6 +11097,22 @@ const char *intel_output_name(int output)
         return names[output];
 }
 
+static bool intel_crt_present(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        if (IS_ULT(dev))
+                return false;
+
+        if (IS_CHERRYVIEW(dev))
+                return false;
+
+        if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
+                return false;
+
+        return true;
+}
+
 static void intel_setup_outputs(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -11095,7 +11121,7 @@ static void intel_setup_outputs(struct drm_device *dev)
 
         intel_lvds_init(dev);
 
-        if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
+        if (intel_crt_present(dev))
                 intel_crt_init(dev);
 
         if (HAS_DDI(dev)) {
@@ -11565,6 +11591,14 @@ static void quirk_invert_brightness(struct drm_device *dev)
         DRM_INFO("applying inverted panel brightness quirk\n");
 }
 
+/* Some VBT's incorrectly indicate no backlight is present */
+static void quirk_backlight_present(struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
+        DRM_INFO("applying backlight present quirk\n");
+}
+
 struct intel_quirk {
         int device;
         int subsystem_vendor;
@@ -11633,6 +11667,15 @@ static struct intel_quirk intel_quirks[] = {
 
         /* Acer Aspire 5336 */
         { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
+
+        /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
+        { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
+
+        /* Toshiba CB35 Chromebook (Celeron 2955U) */
+        { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
+
+        /* HP Chromebook 14 (Celeron 2955U) */
+        { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
 };
 
 static void intel_init_quirks(struct drm_device *dev)
@@ -11871,6 +11914,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
                  * ...  */
                 plane = crtc->plane;
                 crtc->plane = !plane;
+                crtc->primary_enabled = true;
                 dev_priv->display.crtc_disable(&crtc->base);
                 crtc->plane = plane;
 
@@ -12411,8 +12455,8 @@ intel_display_capture_error_state(struct drm_device *dev)
 
         for_each_pipe(i) {
                 error->pipe[i].power_domain_on =
-                        intel_display_power_enabled_sw(dev_priv,
-                                                       POWER_DOMAIN_PIPE(i));
+                        intel_display_power_enabled_unlocked(dev_priv,
+                                                           POWER_DOMAIN_PIPE(i));
                 if (!error->pipe[i].power_domain_on)
                         continue;
 
@@ -12447,7 +12491,7 @@ intel_display_capture_error_state(struct drm_device *dev)
                 enum transcoder cpu_transcoder = transcoders[i];
 
                 error->transcoder[i].power_domain_on =
-                        intel_display_power_enabled_sw(dev_priv,
+                        intel_display_power_enabled_unlocked(dev_priv,
                                 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
                 if (!error->transcoder[i].power_domain_on)
                         continue;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52fda950fd2a..8a1a4fbc06ac 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -28,6 +28,8 @@
 #include <linux/i2c.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <linux/notifier.h>
+#include <linux/reboot.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
@@ -336,6 +338,37 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 }
 
+/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
+   This function only applicable when panel PM state is not to be tracked */
+static int edp_notify_handler(struct notifier_block *this, unsigned long code,
+                              void *unused)
+{
+        struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
+                                                 edp_notifier);
+        struct drm_device *dev = intel_dp_to_dev(intel_dp);
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        u32 pp_div;
+        u32 pp_ctrl_reg, pp_div_reg;
+        enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
+
+        if (!is_edp(intel_dp) || code != SYS_RESTART)
+                return 0;
+
+        if (IS_VALLEYVIEW(dev)) {
+                pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
+                pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
+                pp_div = I915_READ(pp_div_reg);
+                pp_div &= PP_REFERENCE_DIVIDER_MASK;
+
+                /* 0x1F write to PP_DIV_REG sets max cycle delay */
+                I915_WRITE(pp_div_reg, pp_div | 0x1F);
+                I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
+                msleep(intel_dp->panel_power_cycle_delay);
+        }
+
+        return 0;
+}
+
 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 {
         struct drm_device *dev = intel_dp_to_dev(intel_dp);
@@ -873,8 +906,8 @@ intel_dp_compute_config(struct intel_encoder *encoder,
                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
                                                    bpp);
 
-                for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
-                        for (clock = min_clock; clock <= max_clock; clock++) {
+                for (clock = min_clock; clock <= max_clock; clock++) {
+                        for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
                                 link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
                                 link_avail = intel_dp_max_data_rate(link_clock,
                                                                     lane_count);
@@ -3707,6 +3740,10 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
                 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
                 edp_panel_vdd_off_sync(intel_dp);
                 drm_modeset_unlock(&dev->mode_config.connection_mutex);
+                if (intel_dp->edp_notifier.notifier_call) {
+                        unregister_reboot_notifier(&intel_dp->edp_notifier);
+                        intel_dp->edp_notifier.notifier_call = NULL;
+                }
         }
         kfree(intel_dig_port);
 }
@@ -4184,6 +4221,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
         }
         mutex_unlock(&dev->mode_config.mutex);
 
+        if (IS_VALLEYVIEW(dev)) {
+                intel_dp->edp_notifier.notifier_call = edp_notify_handler;
+                register_reboot_notifier(&intel_dp->edp_notifier);
+        }
+
         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
         intel_panel_setup_backlight(connector);
 
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index bda0ae3d80cc..f67340ed2c12 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -538,6 +538,8 @@ struct intel_dp {
         unsigned long last_power_on;
         unsigned long last_backlight_off;
         bool psr_setup_done;
+        struct notifier_block edp_notifier;
+
         bool use_tps3;
         struct intel_connector *attached_connector;
 
@@ -950,8 +952,8 @@ int intel_power_domains_init(struct drm_i915_private *);
 void intel_power_domains_remove(struct drm_i915_private *);
 bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
                                  enum intel_display_power_domain domain);
-bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
-                                    enum intel_display_power_domain domain);
+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
+                                          enum intel_display_power_domain domain);
 void intel_display_power_get(struct drm_i915_private *dev_priv,
                              enum intel_display_power_domain domain);
 void intel_display_power_put(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 02f99d768d49..3fd082933c87 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -117,17 +117,18 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
         /* bandgap reset is needed after everytime we do power gate */
         band_gap_reset(dev_priv);
 
+        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        usleep_range(2500, 3000);
+
         val = I915_READ(MIPI_PORT_CTRL(pipe));
         I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
         usleep_range(1000, 1500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
-        usleep_range(2000, 2500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
-        usleep_range(2000, 2500);
-        I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
-        usleep_range(2000, 2500);
+
+        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
+        usleep_range(2500, 3000);
+
         I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
-        usleep_range(2000, 2500);
+        usleep_range(2500, 3000);
 }
 
 static void intel_dsi_enable(struct intel_encoder *encoder)
@@ -271,23 +272,23 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
 
         DRM_DEBUG_KMS("\n");
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
         usleep_range(2000, 2500);
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
         usleep_range(2000, 2500);
 
-        I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
+        I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
         usleep_range(2000, 2500);
 
-        val = I915_READ(MIPI_PORT_CTRL(pipe));
-        I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
-        usleep_range(1000, 1500);
-
         if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
                                         == 0x00000), 30))
                 DRM_ERROR("DSI LP not going Low\n");
 
+        val = I915_READ(MIPI_PORT_CTRL(pipe));
+        I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
+        usleep_range(1000, 1500);
+
         I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
         usleep_range(2000, 2500);
 
diff --git a/drivers/gpu/drm/i915/intel_dsi_cmd.c b/drivers/gpu/drm/i915/intel_dsi_cmd.c
index 3eeb21b9fddf..933c86305237 100644
--- a/drivers/gpu/drm/i915/intel_dsi_cmd.c
+++ b/drivers/gpu/drm/i915/intel_dsi_cmd.c
@@ -404,12 +404,6 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
         else
                 cmd |= DPI_LP_MODE;
 
-        /* DPI virtual channel?! */
-
-        mask = DPI_FIFO_EMPTY;
-        if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
-                DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
-
         /* clear bit */
         I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 23126023aeba..5e5a72fca5fb 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -111,6 +111,13 @@ static void intel_lvds_get_config(struct intel_encoder *encoder,
 
         pipe_config->adjusted_mode.flags |= flags;
 
+        /* gen2/3 store dither state in pfit control, needs to match */
+        if (INTEL_INFO(dev)->gen < 4) {
+                tmp = I915_READ(PFIT_CONTROL);
+
+                pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
+        }
+
         dotclock = pipe_config->port_clock;
 
         if (HAS_PCH_SPLIT(dev_priv->dev))
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 2e2c71fcc9ed..4f6b53998d79 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -403,6 +403,15 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
 
         DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
 
+        /*
+         * If the acpi_video interface is not supposed to be used, don't
+         * bother processing backlight level change requests from firmware.
+         */
+        if (!acpi_video_verify_backlight_support()) {
+                DRM_DEBUG_KMS("opregion backlight request ignored\n");
+                return 0;
+        }
+
         if (!(bclp & ASLE_BCLP_VALID))
                 return ASLC_BACKLIGHT_FAILED;
 
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 5e6c888b4928..12b02fe1d0ae 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -361,16 +361,16 @@ void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
                 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
                                  PFIT_FILTER_FUZZY);
 
-        /* Make sure pre-965 set dither correctly for 18bpp panels. */
-        if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
-                pfit_control |= PANEL_8TO6_DITHER_ENABLE;
-
 out:
         if ((pfit_control & PFIT_ENABLE) == 0) {
                 pfit_control = 0;
                 pfit_pgm_ratios = 0;
         }
 
+        /* Make sure pre-965 set dither correctly for 18bpp panels. */
+        if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
+                pfit_control |= PANEL_8TO6_DITHER_ENABLE;
+
         pipe_config->gmch_pfit.control = pfit_control;
         pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
         pipe_config->gmch_pfit.lvds_border_bits = border;
@@ -798,9 +798,6 @@ static void i965_enable_backlight(struct intel_connector *connector)
         ctl = freq << 16;
         I915_WRITE(BLC_PWM_CTL, ctl);
 
-        /* XXX: combine this into above write? */
-        intel_panel_actually_set_backlight(connector, panel->backlight.level);
-
         ctl2 = BLM_PIPE(pipe);
         if (panel->backlight.combination_mode)
                 ctl2 |= BLM_COMBINATION_MODE;
@@ -809,6 +806,8 @@ static void i965_enable_backlight(struct intel_connector *connector)
         I915_WRITE(BLC_PWM_CTL2, ctl2);
         POSTING_READ(BLC_PWM_CTL2);
         I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
+
+        intel_panel_actually_set_backlight(connector, panel->backlight.level);
 }
 
 static void vlv_enable_backlight(struct intel_connector *connector)
@@ -1119,8 +1118,12 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
         int ret;
 
         if (!dev_priv->vbt.backlight.present) {
-                DRM_DEBUG_KMS("native backlight control not available per VBT\n");
-                return 0;
+                if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
+                        DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
+                } else {
+                        DRM_DEBUG_KMS("no backlight present per VBT\n");
+                        return 0;
+                }
         }
 
         /* set level and max in panel struct */
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d1e53abec1b5..ee72807069e4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -511,8 +511,7 @@ void intel_update_fbc(struct drm_device *dev)
         obj = intel_fb->obj;
         adjusted_mode = &intel_crtc->config.adjusted_mode;
 
-        if (i915.enable_fbc < 0 &&
-            INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
+        if (i915.enable_fbc < 0) {
                 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
                         DRM_DEBUG_KMS("disabled per chip default\n");
                 goto out_disable;
@@ -3210,6 +3209,14 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 */
 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 {
+        struct drm_device *dev = dev_priv->dev;
+
+        /* Latest VLV doesn't need to force the gfx clock */
+        if (dev->pdev->revision >= 0xd) {
+                valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
+                return;
+        }
+
         /*
          * When we are idle.  Drop to min voltage state.
          */
@@ -3506,15 +3513,11 @@ static void gen8_enable_rps(struct drm_device *dev)
 
         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
 
-        /* WaDisablePwrmtrEvent:chv (pre-production hw) */
-        I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
-        I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
-
         /* 5: Enable RPS */
         I915_WRITE(GEN6_RP_CONTROL,
                    GEN6_RP_MEDIA_TURBO |
                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
-                   GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
+                   GEN6_RP_MEDIA_IS_GFX |
                    GEN6_RP_ENABLE |
                    GEN6_RP_UP_BUSY_AVG |
                    GEN6_RP_DOWN_IDLE_AVG);
@@ -5608,8 +5611,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 }
 
-bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
-                                    enum intel_display_power_domain domain)
+bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv,
+                                          enum intel_display_power_domain domain)
 {
         struct i915_power_domains *power_domains;
         struct i915_power_well *power_well;
@@ -5620,16 +5623,19 @@ bool intel_display_power_enabled_sw(struct drm_i915_private *dev_priv,
                 return false;
 
         power_domains = &dev_priv->power_domains;
+
         is_enabled = true;
+
         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
                 if (power_well->always_on)
                         continue;
 
-                if (!power_well->count) {
+                if (!power_well->hw_enabled) {
                         is_enabled = false;
                         break;
                 }
         }
+
         return is_enabled;
 }
 
@@ -5637,30 +5643,15 @@ bool intel_display_power_enabled(struct drm_i915_private *dev_priv,
                                  enum intel_display_power_domain domain)
 {
         struct i915_power_domains *power_domains;
-        struct i915_power_well *power_well;
-        bool is_enabled;
-        int i;
-
-        if (dev_priv->pm.suspended)
-                return false;
+        bool ret;
 
         power_domains = &dev_priv->power_domains;
 
-        is_enabled = true;
-
         mutex_lock(&power_domains->lock);
-        for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
-                if (power_well->always_on)
-                        continue;
-
-                if (!power_well->ops->is_enabled(dev_priv, power_well)) {
-                        is_enabled = false;
-                        break;
-                }
-        }
+        ret = intel_display_power_enabled_unlocked(dev_priv, domain);
         mutex_unlock(&power_domains->lock);
 
-        return is_enabled;
+        return ret;
 }
 
 /*
@@ -5981,6 +5972,7 @@ void intel_display_power_get(struct drm_i915_private *dev_priv,
                 if (!power_well->count++) {
                         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
                         power_well->ops->enable(dev_priv, power_well);
+                        power_well->hw_enabled = true;
                 }
 
                 check_power_well_state(dev_priv, power_well);
@@ -6010,6 +6002,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 
                 if (!--power_well->count && i915.disable_power_well) {
                         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
+                        power_well->hw_enabled = false;
                         power_well->ops->disable(dev_priv, power_well);
                 }
 
@@ -6024,33 +6017,56 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 static struct i915_power_domains *hsw_pwr;
 
 /* Display audio driver power well request */
-void i915_request_power_well(void)
+int i915_request_power_well(void)
 {
         struct drm_i915_private *dev_priv;
 
-        if (WARN_ON(!hsw_pwr))
-                return;
+        if (!hsw_pwr)
+                return -ENODEV;
 
         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
                                 power_domains);
         intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(i915_request_power_well);
 
 /* Display audio driver power well release */
-void i915_release_power_well(void)
+int i915_release_power_well(void)
 {
         struct drm_i915_private *dev_priv;
 
-        if (WARN_ON(!hsw_pwr))
-                return;
+        if (!hsw_pwr)
+                return -ENODEV;
 
         dev_priv = container_of(hsw_pwr, struct drm_i915_private,
                                 power_domains);
         intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
+        return 0;
 }
 EXPORT_SYMBOL_GPL(i915_release_power_well);
 
+/*
+ * Private interface for the audio driver to get CDCLK in kHz.
+ *
+ * Caller must request power well using i915_request_power_well() prior to
+ * making the call.
+ */
+int i915_get_cdclk_freq(void)
+{
+        struct drm_i915_private *dev_priv;
+
+        if (!hsw_pwr)
+                return -ENODEV;
+
+        dev_priv = container_of(hsw_pwr, struct drm_i915_private,
+                                power_domains);
+
+        return intel_ddi_get_cdclk_freq(dev_priv);
+}
+EXPORT_SYMBOL_GPL(i915_get_cdclk_freq);
+
+
 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
 
 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
@@ -6270,8 +6286,11 @@ static void intel_power_domains_resume(struct drm_i915_private *dev_priv)
         int i;
 
         mutex_lock(&power_domains->lock);
-        for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains)
+        for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
                 power_well->ops->sync_hw(dev_priv, power_well);
+                power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
+                                                                     power_well);
+        }
         mutex_unlock(&power_domains->lock);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 910c83cf7d44..e72017bdcd7f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -55,7 +55,7 @@ struct intel_ring_hangcheck {
         u32 seqno;
         int score;
         enum intel_ring_hangcheck_action action;
-        bool deadlock;
+        int deadlock;
 };
 
 struct intel_ringbuffer {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 6a4d5bc17697..20375cc7f82d 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1385,7 +1385,9 @@ static void intel_sdvo_get_config(struct intel_encoder *encoder,
                          >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
         }
 
-        dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
+        dotclock = pipe_config->port_clock;
+        if (pipe_config->pixel_multiplier)
+                dotclock /= pipe_config->pixel_multiplier;
 
         if (HAS_PCH_SPLIT(dev))
                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1b66ddcdfb33..9a17b4e92ef4 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -691,6 +691,14 @@ intel_post_enable_primary(struct drm_crtc *crtc)
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 
         /*
+         * BDW signals flip done immediately if the plane
+         * is disabled, even if the plane enable is already
+         * armed to occur at the next vblank :(
+         */
+        if (IS_BROADWELL(dev))
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
+
+        /*
          * FIXME IPS should be fine as long as one plane is
          * enabled, but in practice it seems to have problems
          * when going from primary only to sprite only and vice
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 79cba593df0d..4f6fef7ac069 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -320,7 +320,8 @@ static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
         struct drm_i915_private *dev_priv = dev->dev_private;
         unsigned long irqflags;
 
-        del_timer_sync(&dev_priv->uncore.force_wake_timer);
+        if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
+                gen6_force_wake_timer((unsigned long)dev_priv);
 
         /* Hold uncore.lock across reset to prevent any register access
          * with forcewake not set correctly