Merge branch 'drm-intel-fixes' into drm-intel-next

2 files changed, 18 insertions, 6 deletions

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 52b79d9d5d2d..6a9ec00f8c81 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1335,10 +1335,16 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
         u32 reg;
         uint32_t DP = intel_dp->DP;
 
-        /* Enable output, wait for it to become active */
-        I915_WRITE(intel_dp->output_reg, intel_dp->DP);
-        POSTING_READ(intel_dp->output_reg);
-        intel_wait_for_vblank(dev, intel_crtc->pipe);
+        /*
+         * On CPT we have to enable the port in training pattern 1, which
+         * will happen below in intel_dp_set_link_train.  Otherwise, enable
+         * the port and wait for it to become active.
+         */
+        if (!HAS_PCH_CPT(dev)) {
+                I915_WRITE(intel_dp->output_reg, intel_dp->DP);
+                POSTING_READ(intel_dp->output_reg);
+                intel_wait_for_vblank(dev, intel_crtc->pipe);
+        }
 
         /* Write the link configuration data */
         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
@@ -1371,7 +1377,8 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
                         reg = DP | DP_LINK_TRAIN_PAT_1;
 
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_1))
+                                             DP_TRAINING_PATTERN_1 |
+                                             DP_LINK_SCRAMBLING_DISABLE))
                         break;
                 /* Set training pattern 1 */
 
@@ -1446,7 +1453,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
 
                 /* channel eq pattern */
                 if (!intel_dp_set_link_train(intel_dp, reg,
-                                             DP_TRAINING_PATTERN_2))
+                                             DP_TRAINING_PATTERN_2 |
+                                             DP_LINK_SCRAMBLING_DISABLE))
                         break;
 
                 udelay(400);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index a06ff07a4d3b..05f500cd9c24 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -83,11 +83,15 @@ intel_pch_panel_fitting(struct drm_device *dev,
                         u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
                         if (scaled_width > scaled_height) { /* pillar */
                                 width = scaled_height / mode->vdisplay;
+                                if (width & 1)
+                                        width++;
                                 x = (adjusted_mode->hdisplay - width + 1) / 2;
                                 y = 0;
                                 height = adjusted_mode->vdisplay;
                         } else if (scaled_width < scaled_height) { /* letter */
                                 height = scaled_width / mode->hdisplay;
+                                if (height & 1)
+                                    height++;
                                 y = (adjusted_mode->vdisplay - height + 1) / 2;
                                 x = 0;
                                 width = adjusted_mode->hdisplay;