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authorVille Syrjälä <ville.syrjala@linux.intel.com>2014-02-14 07:18:57 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-03-07 16:36:58 -0500
commit922044c9dfec40d5adc5d4a757f802e55e3d0a85 (patch)
tree5e3700d4f1837b652b600038c32da3a4c9efeceb /drivers/gpu/drm/i915
parent77961eb984c7e5394bd29cc7be2ab0bf0cc7e7b1 (diff)
drm/i915: Avoid div by zero when pixel clock is large
Make sure the line_time_us isn't zero in the gmch watermarks code as that would cause a div by zero. This can be triggered by specifying a very fast pixel clock for the mode. At some point we should probably just switch over to using the same math we use on PCH platforms which avoids such intermediate rounded results. Also we should verify the user provided mode much more rigorously. At the moment we accept pretty much anything. Note that "very fast mode" here means above 74.25 GHz. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Add Ville's clarification of what "very fast" means.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 030880a2cf4e..fc96e611a8a7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1134,7 +1134,7 @@ static bool g4x_compute_wm0(struct drm_device *dev,
1134 *plane_wm = display->max_wm; 1134 *plane_wm = display->max_wm;
1135 1135
1136 /* Use the large buffer method to calculate cursor watermark */ 1136 /* Use the large buffer method to calculate cursor watermark */
1137 line_time_us = ((htotal * 1000) / clock); 1137 line_time_us = max(htotal * 1000 / clock, 1);
1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; 1138 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1139 entries = line_count * 64 * pixel_size; 1139 entries = line_count * 64 * pixel_size;
1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; 1140 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
@@ -1210,7 +1210,7 @@ static bool g4x_compute_srwm(struct drm_device *dev,
1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; 1210 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
1211 pixel_size = crtc->fb->bits_per_pixel / 8; 1211 pixel_size = crtc->fb->bits_per_pixel / 8;
1212 1212
1213 line_time_us = (htotal * 1000) / clock; 1213 line_time_us = max(htotal * 1000 / clock, 1);
1214 line_count = (latency_ns / line_time_us + 1000) / 1000; 1214 line_count = (latency_ns / line_time_us + 1000) / 1000;
1215 line_size = hdisplay * pixel_size; 1215 line_size = hdisplay * pixel_size;
1216 1216
@@ -1443,7 +1443,7 @@ static void i965_update_wm(struct drm_crtc *unused_crtc)
1443 unsigned long line_time_us; 1443 unsigned long line_time_us;
1444 int entries; 1444 int entries;
1445 1445
1446 line_time_us = ((htotal * 1000) / clock); 1446 line_time_us = max(htotal * 1000 / clock, 1);
1447 1447
1448 /* Use ns/us then divide to preserve precision */ 1448 /* Use ns/us then divide to preserve precision */
1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1449 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
@@ -1569,7 +1569,7 @@ static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1569 unsigned long line_time_us; 1569 unsigned long line_time_us;
1570 int entries; 1570 int entries;
1571 1571
1572 line_time_us = (htotal * 1000) / clock; 1572 line_time_us = max(htotal * 1000 / clock, 1);
1573 1573
1574 /* Use ns/us then divide to preserve precision */ 1574 /* Use ns/us then divide to preserve precision */
1575 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * 1575 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *