diff options
author | Ingo Molnar <mingo@kernel.org> | 2014-05-22 04:28:56 -0400 |
---|---|---|
committer | Ingo Molnar <mingo@kernel.org> | 2014-05-22 04:28:56 -0400 |
commit | 65c2ce70046c779974af8b5dfc25a0df489089b5 (patch) | |
tree | b16f152eb62b71cf5a1edc51da865b357c989922 /drivers/gpu/drm/i915 | |
parent | 842514849a616e9b61acad65771c7afe01e651f9 (diff) | |
parent | 4b660a7f5c8099d88d1a43d8ae138965112592c7 (diff) |
Merge tag 'v3.15-rc6' into sched/core, to pick up the latest fixes
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/i915_drv.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_gem_gtt.c | 32 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 18 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_bios.c | 52 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 49 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 69 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_fbdev.c | 19 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 9 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_panel.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 40 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 54 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_sdvo.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_uncore.c | 2 |
16 files changed, 280 insertions, 84 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ec82f6bff122..108e1ec2fa4b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h | |||
@@ -1954,6 +1954,9 @@ struct drm_i915_cmd_table { | |||
1954 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) | 1954 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
1955 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ | 1955 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
1956 | ((dev)->pdev->device & 0x00F0) == 0x0020) | 1956 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
1957 | /* ULX machines are also considered ULT. */ | ||
1958 | #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \ | ||
1959 | (dev)->pdev->device == 0x0A1E) | ||
1957 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) | 1960 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
1958 | 1961 | ||
1959 | /* | 1962 | /* |
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index ab5e93c30aa2..154b0f8bb88d 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c | |||
@@ -34,25 +34,35 @@ static void gen8_setup_private_ppat(struct drm_i915_private *dev_priv); | |||
34 | 34 | ||
35 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) | 35 | bool intel_enable_ppgtt(struct drm_device *dev, bool full) |
36 | { | 36 | { |
37 | if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | 37 | if (i915.enable_ppgtt == 0) |
38 | return false; | 38 | return false; |
39 | 39 | ||
40 | if (i915.enable_ppgtt == 1 && full) | 40 | if (i915.enable_ppgtt == 1 && full) |
41 | return false; | 41 | return false; |
42 | 42 | ||
43 | return true; | ||
44 | } | ||
45 | |||
46 | static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) | ||
47 | { | ||
48 | if (enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) | ||
49 | return 0; | ||
50 | |||
51 | if (enable_ppgtt == 1) | ||
52 | return 1; | ||
53 | |||
54 | if (enable_ppgtt == 2 && HAS_PPGTT(dev)) | ||
55 | return 2; | ||
56 | |||
43 | #ifdef CONFIG_INTEL_IOMMU | 57 | #ifdef CONFIG_INTEL_IOMMU |
44 | /* Disable ppgtt on SNB if VT-d is on. */ | 58 | /* Disable ppgtt on SNB if VT-d is on. */ |
45 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | 59 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { |
46 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | 60 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); |
47 | return false; | 61 | return 0; |
48 | } | 62 | } |
49 | #endif | 63 | #endif |
50 | 64 | ||
51 | /* Full ppgtt disabled by default for now due to issues. */ | 65 | return HAS_ALIASING_PPGTT(dev) ? 1 : 0; |
52 | if (full) | ||
53 | return false; /* HAS_PPGTT(dev) */ | ||
54 | else | ||
55 | return HAS_ALIASING_PPGTT(dev); | ||
56 | } | 66 | } |
57 | 67 | ||
58 | #define GEN6_PPGTT_PD_ENTRIES 512 | 68 | #define GEN6_PPGTT_PD_ENTRIES 512 |
@@ -2031,6 +2041,14 @@ int i915_gem_gtt_init(struct drm_device *dev) | |||
2031 | gtt->base.total >> 20); | 2041 | gtt->base.total >> 20); |
2032 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); | 2042 | DRM_DEBUG_DRIVER("GMADR size = %ldM\n", gtt->mappable_end >> 20); |
2033 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); | 2043 | DRM_DEBUG_DRIVER("GTT stolen size = %zdM\n", gtt->stolen_size >> 20); |
2044 | /* | ||
2045 | * i915.enable_ppgtt is read-only, so do an early pass to validate the | ||
2046 | * user's requested state against the hardware/driver capabilities. We | ||
2047 | * do this now so that we can print out any log messages once rather | ||
2048 | * than every time we check intel_enable_ppgtt(). | ||
2049 | */ | ||
2050 | i915.enable_ppgtt = sanitize_enable_ppgtt(dev, i915.enable_ppgtt); | ||
2051 | DRM_DEBUG_DRIVER("ppgtt mode: %i\n", i915.enable_ppgtt); | ||
2034 | 2052 | ||
2035 | return 0; | 2053 | return 0; |
2036 | } | 2054 | } |
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7753249b3a95..f98ba4e6e70b 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -1362,10 +1362,20 @@ static inline void intel_hpd_irq_handler(struct drm_device *dev, | |||
1362 | spin_lock(&dev_priv->irq_lock); | 1362 | spin_lock(&dev_priv->irq_lock); |
1363 | for (i = 1; i < HPD_NUM_PINS; i++) { | 1363 | for (i = 1; i < HPD_NUM_PINS; i++) { |
1364 | 1364 | ||
1365 | WARN_ONCE(hpd[i] & hotplug_trigger && | 1365 | if (hpd[i] & hotplug_trigger && |
1366 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED, | 1366 | dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) { |
1367 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | 1367 | /* |
1368 | hotplug_trigger, i, hpd[i]); | 1368 | * On GMCH platforms the interrupt mask bits only |
1369 | * prevent irq generation, not the setting of the | ||
1370 | * hotplug bits itself. So only WARN about unexpected | ||
1371 | * interrupts on saner platforms. | ||
1372 | */ | ||
1373 | WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev), | ||
1374 | "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n", | ||
1375 | hotplug_trigger, i, hpd[i]); | ||
1376 | |||
1377 | continue; | ||
1378 | } | ||
1369 | 1379 | ||
1370 | if (!(hpd[i] & hotplug_trigger) || | 1380 | if (!(hpd[i] & hotplug_trigger) || |
1371 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) | 1381 | dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED) |
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9f5b18d9d885..c77af69c2d8f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -827,6 +827,7 @@ enum punit_power_well { | |||
827 | # define MI_FLUSH_ENABLE (1 << 12) | 827 | # define MI_FLUSH_ENABLE (1 << 12) |
828 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) | 828 | # define ASYNC_FLIP_PERF_DISABLE (1 << 14) |
829 | # define MODE_IDLE (1 << 9) | 829 | # define MODE_IDLE (1 << 9) |
830 | # define STOP_RING (1 << 8) | ||
830 | 831 | ||
831 | #define GEN6_GT_MODE 0x20d0 | 832 | #define GEN6_GT_MODE 0x20d0 |
832 | #define GEN7_GT_MODE 0x7008 | 833 | #define GEN7_GT_MODE 0x7008 |
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c index fa486c5fbb02..aff4a113cda3 100644 --- a/drivers/gpu/drm/i915/intel_bios.c +++ b/drivers/gpu/drm/i915/intel_bios.c | |||
@@ -560,47 +560,71 @@ parse_edp(struct drm_i915_private *dev_priv, struct bdb_header *bdb) | |||
560 | 560 | ||
561 | dev_priv->vbt.edp_pps = *edp_pps; | 561 | dev_priv->vbt.edp_pps = *edp_pps; |
562 | 562 | ||
563 | dev_priv->vbt.edp_rate = edp_link_params->rate ? DP_LINK_BW_2_7 : | 563 | switch (edp_link_params->rate) { |
564 | DP_LINK_BW_1_62; | 564 | case EDP_RATE_1_62: |
565 | dev_priv->vbt.edp_rate = DP_LINK_BW_1_62; | ||
566 | break; | ||
567 | case EDP_RATE_2_7: | ||
568 | dev_priv->vbt.edp_rate = DP_LINK_BW_2_7; | ||
569 | break; | ||
570 | default: | ||
571 | DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", | ||
572 | edp_link_params->rate); | ||
573 | break; | ||
574 | } | ||
575 | |||
565 | switch (edp_link_params->lanes) { | 576 | switch (edp_link_params->lanes) { |
566 | case 0: | 577 | case EDP_LANE_1: |
567 | dev_priv->vbt.edp_lanes = 1; | 578 | dev_priv->vbt.edp_lanes = 1; |
568 | break; | 579 | break; |
569 | case 1: | 580 | case EDP_LANE_2: |
570 | dev_priv->vbt.edp_lanes = 2; | 581 | dev_priv->vbt.edp_lanes = 2; |
571 | break; | 582 | break; |
572 | case 3: | 583 | case EDP_LANE_4: |
573 | default: | ||
574 | dev_priv->vbt.edp_lanes = 4; | 584 | dev_priv->vbt.edp_lanes = 4; |
575 | break; | 585 | break; |
586 | default: | ||
587 | DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", | ||
588 | edp_link_params->lanes); | ||
589 | break; | ||
576 | } | 590 | } |
591 | |||
577 | switch (edp_link_params->preemphasis) { | 592 | switch (edp_link_params->preemphasis) { |
578 | case 0: | 593 | case EDP_PREEMPHASIS_NONE: |
579 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0; | 594 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_0; |
580 | break; | 595 | break; |
581 | case 1: | 596 | case EDP_PREEMPHASIS_3_5dB: |
582 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5; | 597 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_3_5; |
583 | break; | 598 | break; |
584 | case 2: | 599 | case EDP_PREEMPHASIS_6dB: |
585 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6; | 600 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_6; |
586 | break; | 601 | break; |
587 | case 3: | 602 | case EDP_PREEMPHASIS_9_5dB: |
588 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5; | 603 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPHASIS_9_5; |
589 | break; | 604 | break; |
605 | default: | ||
606 | DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", | ||
607 | edp_link_params->preemphasis); | ||
608 | break; | ||
590 | } | 609 | } |
610 | |||
591 | switch (edp_link_params->vswing) { | 611 | switch (edp_link_params->vswing) { |
592 | case 0: | 612 | case EDP_VSWING_0_4V: |
593 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400; | 613 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_400; |
594 | break; | 614 | break; |
595 | case 1: | 615 | case EDP_VSWING_0_6V: |
596 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600; | 616 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_600; |
597 | break; | 617 | break; |
598 | case 2: | 618 | case EDP_VSWING_0_8V: |
599 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800; | 619 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_800; |
600 | break; | 620 | break; |
601 | case 3: | 621 | case EDP_VSWING_1_2V: |
602 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200; | 622 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_1200; |
603 | break; | 623 | break; |
624 | default: | ||
625 | DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", | ||
626 | edp_link_params->vswing); | ||
627 | break; | ||
604 | } | 628 | } |
605 | } | 629 | } |
606 | 630 | ||
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index dae976f51d83..48aa516a1ac0 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -9654,11 +9654,22 @@ intel_pipe_config_compare(struct drm_device *dev, | |||
9654 | PIPE_CONF_CHECK_I(pipe_src_w); | 9654 | PIPE_CONF_CHECK_I(pipe_src_w); |
9655 | PIPE_CONF_CHECK_I(pipe_src_h); | 9655 | PIPE_CONF_CHECK_I(pipe_src_h); |
9656 | 9656 | ||
9657 | PIPE_CONF_CHECK_I(gmch_pfit.control); | 9657 | /* |
9658 | /* pfit ratios are autocomputed by the hw on gen4+ */ | 9658 | * FIXME: BIOS likes to set up a cloned config with lvds+external |
9659 | if (INTEL_INFO(dev)->gen < 4) | 9659 | * screen. Since we don't yet re-compute the pipe config when moving |
9660 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | 9660 | * just the lvds port away to another pipe the sw tracking won't match. |
9661 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | 9661 | * |
9662 | * Proper atomic modesets with recomputed global state will fix this. | ||
9663 | * Until then just don't check gmch state for inherited modes. | ||
9664 | */ | ||
9665 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | ||
9666 | PIPE_CONF_CHECK_I(gmch_pfit.control); | ||
9667 | /* pfit ratios are autocomputed by the hw on gen4+ */ | ||
9668 | if (INTEL_INFO(dev)->gen < 4) | ||
9669 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | ||
9670 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | ||
9671 | } | ||
9672 | |||
9662 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | 9673 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
9663 | if (current_config->pch_pfit.enabled) { | 9674 | if (current_config->pch_pfit.enabled) { |
9664 | PIPE_CONF_CHECK_I(pch_pfit.pos); | 9675 | PIPE_CONF_CHECK_I(pch_pfit.pos); |
@@ -11384,15 +11395,6 @@ void intel_modeset_init(struct drm_device *dev) | |||
11384 | } | 11395 | } |
11385 | } | 11396 | } |
11386 | 11397 | ||
11387 | static void | ||
11388 | intel_connector_break_all_links(struct intel_connector *connector) | ||
11389 | { | ||
11390 | connector->base.dpms = DRM_MODE_DPMS_OFF; | ||
11391 | connector->base.encoder = NULL; | ||
11392 | connector->encoder->connectors_active = false; | ||
11393 | connector->encoder->base.crtc = NULL; | ||
11394 | } | ||
11395 | |||
11396 | static void intel_enable_pipe_a(struct drm_device *dev) | 11398 | static void intel_enable_pipe_a(struct drm_device *dev) |
11397 | { | 11399 | { |
11398 | struct intel_connector *connector; | 11400 | struct intel_connector *connector; |
@@ -11474,8 +11476,17 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) | |||
11474 | if (connector->encoder->base.crtc != &crtc->base) | 11476 | if (connector->encoder->base.crtc != &crtc->base) |
11475 | continue; | 11477 | continue; |
11476 | 11478 | ||
11477 | intel_connector_break_all_links(connector); | 11479 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
11480 | connector->base.encoder = NULL; | ||
11478 | } | 11481 | } |
11482 | /* multiple connectors may have the same encoder: | ||
11483 | * handle them and break crtc link separately */ | ||
11484 | list_for_each_entry(connector, &dev->mode_config.connector_list, | ||
11485 | base.head) | ||
11486 | if (connector->encoder->base.crtc == &crtc->base) { | ||
11487 | connector->encoder->base.crtc = NULL; | ||
11488 | connector->encoder->connectors_active = false; | ||
11489 | } | ||
11479 | 11490 | ||
11480 | WARN_ON(crtc->active); | 11491 | WARN_ON(crtc->active); |
11481 | crtc->base.enabled = false; | 11492 | crtc->base.enabled = false; |
@@ -11557,6 +11568,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) | |||
11557 | drm_get_encoder_name(&encoder->base)); | 11568 | drm_get_encoder_name(&encoder->base)); |
11558 | encoder->disable(encoder); | 11569 | encoder->disable(encoder); |
11559 | } | 11570 | } |
11571 | encoder->base.crtc = NULL; | ||
11572 | encoder->connectors_active = false; | ||
11560 | 11573 | ||
11561 | /* Inconsistent output/port/pipe state happens presumably due to | 11574 | /* Inconsistent output/port/pipe state happens presumably due to |
11562 | * a bug in one of the get_hw_state functions. Or someplace else | 11575 | * a bug in one of the get_hw_state functions. Or someplace else |
@@ -11567,8 +11580,8 @@ static void intel_sanitize_encoder(struct intel_encoder *encoder) | |||
11567 | base.head) { | 11580 | base.head) { |
11568 | if (connector->encoder != encoder) | 11581 | if (connector->encoder != encoder) |
11569 | continue; | 11582 | continue; |
11570 | 11583 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
11571 | intel_connector_break_all_links(connector); | 11584 | connector->base.encoder = NULL; |
11572 | } | 11585 | } |
11573 | } | 11586 | } |
11574 | /* Enabled encoders without active connectors will be fixed in | 11587 | /* Enabled encoders without active connectors will be fixed in |
@@ -11616,6 +11629,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev) | |||
11616 | base.head) { | 11629 | base.head) { |
11617 | memset(&crtc->config, 0, sizeof(crtc->config)); | 11630 | memset(&crtc->config, 0, sizeof(crtc->config)); |
11618 | 11631 | ||
11632 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; | ||
11633 | |||
11619 | crtc->active = dev_priv->display.get_pipe_config(crtc, | 11634 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
11620 | &crtc->config); | 11635 | &crtc->config); |
11621 | 11636 | ||
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d2a55884ad52..2a00cb828d20 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -105,7 +105,8 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) | |||
105 | case DP_LINK_BW_2_7: | 105 | case DP_LINK_BW_2_7: |
106 | break; | 106 | break; |
107 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ | 107 | case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */ |
108 | if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) && | 108 | if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || |
109 | INTEL_INFO(dev)->gen >= 8) && | ||
109 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) | 110 | intel_dp->dpcd[DP_DPCD_REV] >= 0x12) |
110 | max_link_bw = DP_LINK_BW_5_4; | 111 | max_link_bw = DP_LINK_BW_5_4; |
111 | else | 112 | else |
@@ -120,6 +121,22 @@ intel_dp_max_link_bw(struct intel_dp *intel_dp) | |||
120 | return max_link_bw; | 121 | return max_link_bw; |
121 | } | 122 | } |
122 | 123 | ||
124 | static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp) | ||
125 | { | ||
126 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | ||
127 | struct drm_device *dev = intel_dig_port->base.base.dev; | ||
128 | u8 source_max, sink_max; | ||
129 | |||
130 | source_max = 4; | ||
131 | if (HAS_DDI(dev) && intel_dig_port->port == PORT_A && | ||
132 | (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0) | ||
133 | source_max = 2; | ||
134 | |||
135 | sink_max = drm_dp_max_lane_count(intel_dp->dpcd); | ||
136 | |||
137 | return min(source_max, sink_max); | ||
138 | } | ||
139 | |||
123 | /* | 140 | /* |
124 | * The units on the numbers in the next two are... bizarre. Examples will | 141 | * The units on the numbers in the next two are... bizarre. Examples will |
125 | * make it clearer; this one parallels an example in the eDP spec. | 142 | * make it clearer; this one parallels an example in the eDP spec. |
@@ -170,7 +187,7 @@ intel_dp_mode_valid(struct drm_connector *connector, | |||
170 | } | 187 | } |
171 | 188 | ||
172 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); | 189 | max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
173 | max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); | 190 | max_lanes = intel_dp_max_lane_count(intel_dp); |
174 | 191 | ||
175 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); | 192 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
176 | mode_rate = intel_dp_link_required(target_clock, 18); | 193 | mode_rate = intel_dp_link_required(target_clock, 18); |
@@ -750,8 +767,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
750 | struct intel_crtc *intel_crtc = encoder->new_crtc; | 767 | struct intel_crtc *intel_crtc = encoder->new_crtc; |
751 | struct intel_connector *intel_connector = intel_dp->attached_connector; | 768 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
752 | int lane_count, clock; | 769 | int lane_count, clock; |
753 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); | 770 | int min_lane_count = 1; |
771 | int max_lane_count = intel_dp_max_lane_count(intel_dp); | ||
754 | /* Conveniently, the link BW constants become indices with a shift...*/ | 772 | /* Conveniently, the link BW constants become indices with a shift...*/ |
773 | int min_clock = 0; | ||
755 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; | 774 | int max_clock = intel_dp_max_link_bw(intel_dp) >> 3; |
756 | int bpp, mode_rate; | 775 | int bpp, mode_rate; |
757 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; | 776 | static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 }; |
@@ -784,19 +803,38 @@ intel_dp_compute_config(struct intel_encoder *encoder, | |||
784 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 | 803 | /* Walk through all bpp values. Luckily they're all nicely spaced with 2 |
785 | * bpc in between. */ | 804 | * bpc in between. */ |
786 | bpp = pipe_config->pipe_bpp; | 805 | bpp = pipe_config->pipe_bpp; |
787 | if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp && | 806 | if (is_edp(intel_dp)) { |
788 | dev_priv->vbt.edp_bpp < bpp) { | 807 | if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) { |
789 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", | 808 | DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", |
790 | dev_priv->vbt.edp_bpp); | 809 | dev_priv->vbt.edp_bpp); |
791 | bpp = dev_priv->vbt.edp_bpp; | 810 | bpp = dev_priv->vbt.edp_bpp; |
811 | } | ||
812 | |||
813 | if (IS_BROADWELL(dev)) { | ||
814 | /* Yes, it's an ugly hack. */ | ||
815 | min_lane_count = max_lane_count; | ||
816 | DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n", | ||
817 | min_lane_count); | ||
818 | } else if (dev_priv->vbt.edp_lanes) { | ||
819 | min_lane_count = min(dev_priv->vbt.edp_lanes, | ||
820 | max_lane_count); | ||
821 | DRM_DEBUG_KMS("using min %u lanes per VBT\n", | ||
822 | min_lane_count); | ||
823 | } | ||
824 | |||
825 | if (dev_priv->vbt.edp_rate) { | ||
826 | min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock); | ||
827 | DRM_DEBUG_KMS("using min %02x link bw per VBT\n", | ||
828 | bws[min_clock]); | ||
829 | } | ||
792 | } | 830 | } |
793 | 831 | ||
794 | for (; bpp >= 6*3; bpp -= 2*3) { | 832 | for (; bpp >= 6*3; bpp -= 2*3) { |
795 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, | 833 | mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, |
796 | bpp); | 834 | bpp); |
797 | 835 | ||
798 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { | 836 | for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) { |
799 | for (clock = 0; clock <= max_clock; clock++) { | 837 | for (clock = min_clock; clock <= max_clock; clock++) { |
800 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); | 838 | link_clock = drm_dp_bw_code_to_link_rate(bws[clock]); |
801 | link_avail = intel_dp_max_data_rate(link_clock, | 839 | link_avail = intel_dp_max_data_rate(link_clock, |
802 | lane_count); | 840 | lane_count); |
@@ -3619,7 +3657,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, | |||
3619 | { | 3657 | { |
3620 | struct drm_connector *connector = &intel_connector->base; | 3658 | struct drm_connector *connector = &intel_connector->base; |
3621 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); | 3659 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3622 | struct drm_device *dev = intel_dig_port->base.base.dev; | 3660 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
3661 | struct drm_device *dev = intel_encoder->base.dev; | ||
3623 | struct drm_i915_private *dev_priv = dev->dev_private; | 3662 | struct drm_i915_private *dev_priv = dev->dev_private; |
3624 | struct drm_display_mode *fixed_mode = NULL; | 3663 | struct drm_display_mode *fixed_mode = NULL; |
3625 | bool has_dpcd; | 3664 | bool has_dpcd; |
@@ -3629,6 +3668,14 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, | |||
3629 | if (!is_edp(intel_dp)) | 3668 | if (!is_edp(intel_dp)) |
3630 | return true; | 3669 | return true; |
3631 | 3670 | ||
3671 | /* The VDD bit needs a power domain reference, so if the bit is already | ||
3672 | * enabled when we boot, grab this reference. */ | ||
3673 | if (edp_have_panel_vdd(intel_dp)) { | ||
3674 | enum intel_display_power_domain power_domain; | ||
3675 | power_domain = intel_display_port_power_domain(intel_encoder); | ||
3676 | intel_display_power_get(dev_priv, power_domain); | ||
3677 | } | ||
3678 | |||
3632 | /* Cache DPCD and EDID for edp. */ | 3679 | /* Cache DPCD and EDID for edp. */ |
3633 | intel_edp_panel_vdd_on(intel_dp); | 3680 | intel_edp_panel_vdd_on(intel_dp); |
3634 | has_dpcd = intel_dp_get_dpcd(intel_dp); | 3681 | has_dpcd = intel_dp_get_dpcd(intel_dp); |
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 0542de982260..328b1a70264b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h | |||
@@ -236,7 +236,8 @@ struct intel_crtc_config { | |||
236 | * tracked with quirk flags so that fastboot and state checker can act | 236 | * tracked with quirk flags so that fastboot and state checker can act |
237 | * accordingly. | 237 | * accordingly. |
238 | */ | 238 | */ |
239 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ | 239 | #define PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS (1<<0) /* unreliable sync mode.flags */ |
240 | #define PIPE_CONFIG_QUIRK_INHERITED_MODE (1<<1) /* mode inherited from firmware */ | ||
240 | unsigned long quirks; | 241 | unsigned long quirks; |
241 | 242 | ||
242 | /* User requested mode, only valid as a starting point to | 243 | /* User requested mode, only valid as a starting point to |
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c index b4d44e62f0c7..f73ba5e6b7a8 100644 --- a/drivers/gpu/drm/i915/intel_fbdev.c +++ b/drivers/gpu/drm/i915/intel_fbdev.c | |||
@@ -132,6 +132,16 @@ static int intelfb_create(struct drm_fb_helper *helper, | |||
132 | 132 | ||
133 | mutex_lock(&dev->struct_mutex); | 133 | mutex_lock(&dev->struct_mutex); |
134 | 134 | ||
135 | if (intel_fb && | ||
136 | (sizes->fb_width > intel_fb->base.width || | ||
137 | sizes->fb_height > intel_fb->base.height)) { | ||
138 | DRM_DEBUG_KMS("BIOS fb too small (%dx%d), we require (%dx%d)," | ||
139 | " releasing it\n", | ||
140 | intel_fb->base.width, intel_fb->base.height, | ||
141 | sizes->fb_width, sizes->fb_height); | ||
142 | drm_framebuffer_unreference(&intel_fb->base); | ||
143 | intel_fb = ifbdev->fb = NULL; | ||
144 | } | ||
135 | if (!intel_fb || WARN_ON(!intel_fb->obj)) { | 145 | if (!intel_fb || WARN_ON(!intel_fb->obj)) { |
136 | DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n"); | 146 | DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n"); |
137 | ret = intelfb_alloc(helper, sizes); | 147 | ret = intelfb_alloc(helper, sizes); |
@@ -377,6 +387,15 @@ static bool intel_fb_initial_config(struct drm_fb_helper *fb_helper, | |||
377 | height); | 387 | height); |
378 | } | 388 | } |
379 | 389 | ||
390 | /* No preferred mode marked by the EDID? Are there any modes? */ | ||
391 | if (!modes[i] && !list_empty(&connector->modes)) { | ||
392 | DRM_DEBUG_KMS("using first mode listed on connector %s\n", | ||
393 | drm_get_connector_name(connector)); | ||
394 | modes[i] = list_first_entry(&connector->modes, | ||
395 | struct drm_display_mode, | ||
396 | head); | ||
397 | } | ||
398 | |||
380 | /* last resort: use current mode */ | 399 | /* last resort: use current mode */ |
381 | if (!modes[i]) { | 400 | if (!modes[i]) { |
382 | /* | 401 | /* |
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index b0413e190625..157267aa3561 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -821,11 +821,11 @@ static void intel_disable_hdmi(struct intel_encoder *encoder) | |||
821 | } | 821 | } |
822 | } | 822 | } |
823 | 823 | ||
824 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi) | 824 | static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit) |
825 | { | 825 | { |
826 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | 826 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); |
827 | 827 | ||
828 | if (!hdmi->has_hdmi_sink || IS_G4X(dev)) | 828 | if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev)) |
829 | return 165000; | 829 | return 165000; |
830 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) | 830 | else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) |
831 | return 300000; | 831 | return 300000; |
@@ -837,7 +837,8 @@ static enum drm_mode_status | |||
837 | intel_hdmi_mode_valid(struct drm_connector *connector, | 837 | intel_hdmi_mode_valid(struct drm_connector *connector, |
838 | struct drm_display_mode *mode) | 838 | struct drm_display_mode *mode) |
839 | { | 839 | { |
840 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) | 840 | if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector), |
841 | true)) | ||
841 | return MODE_CLOCK_HIGH; | 842 | return MODE_CLOCK_HIGH; |
842 | if (mode->clock < 20000) | 843 | if (mode->clock < 20000) |
843 | return MODE_CLOCK_LOW; | 844 | return MODE_CLOCK_LOW; |
@@ -879,7 +880,7 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
879 | struct drm_device *dev = encoder->base.dev; | 880 | struct drm_device *dev = encoder->base.dev; |
880 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | 881 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
881 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; | 882 | int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2; |
882 | int portclock_limit = hdmi_portclock_limit(intel_hdmi); | 883 | int portclock_limit = hdmi_portclock_limit(intel_hdmi, false); |
883 | int desired_bpp; | 884 | int desired_bpp; |
884 | 885 | ||
885 | if (intel_hdmi->color_range_auto) { | 886 | if (intel_hdmi->color_range_auto) { |
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c index 0eead16aeda7..cb8cfb7e0974 100644 --- a/drivers/gpu/drm/i915/intel_panel.c +++ b/drivers/gpu/drm/i915/intel_panel.c | |||
@@ -492,6 +492,7 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level, | |||
492 | enum pipe pipe = intel_get_pipe_from_connector(connector); | 492 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
493 | u32 freq; | 493 | u32 freq; |
494 | unsigned long flags; | 494 | unsigned long flags; |
495 | u64 n; | ||
495 | 496 | ||
496 | if (!panel->backlight.present || pipe == INVALID_PIPE) | 497 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
497 | return; | 498 | return; |
@@ -502,10 +503,9 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level, | |||
502 | 503 | ||
503 | /* scale to hardware max, but be careful to not overflow */ | 504 | /* scale to hardware max, but be careful to not overflow */ |
504 | freq = panel->backlight.max; | 505 | freq = panel->backlight.max; |
505 | if (freq < max) | 506 | n = (u64)level * freq; |
506 | level = level * freq / max; | 507 | do_div(n, max); |
507 | else | 508 | level = n; |
508 | level = freq / max * level; | ||
509 | 509 | ||
510 | panel->backlight.level = level; | 510 | panel->backlight.level = level; |
511 | if (panel->backlight.device) | 511 | if (panel->backlight.device) |
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 19e94c3edc19..d93dcf683e8c 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c | |||
@@ -2095,6 +2095,43 @@ static void intel_print_wm_latency(struct drm_device *dev, | |||
2095 | } | 2095 | } |
2096 | } | 2096 | } |
2097 | 2097 | ||
2098 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, | ||
2099 | uint16_t wm[5], uint16_t min) | ||
2100 | { | ||
2101 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | ||
2102 | |||
2103 | if (wm[0] >= min) | ||
2104 | return false; | ||
2105 | |||
2106 | wm[0] = max(wm[0], min); | ||
2107 | for (level = 1; level <= max_level; level++) | ||
2108 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | ||
2109 | |||
2110 | return true; | ||
2111 | } | ||
2112 | |||
2113 | static void snb_wm_latency_quirk(struct drm_device *dev) | ||
2114 | { | ||
2115 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
2116 | bool changed; | ||
2117 | |||
2118 | /* | ||
2119 | * The BIOS provided WM memory latency values are often | ||
2120 | * inadequate for high resolution displays. Adjust them. | ||
2121 | */ | ||
2122 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | ||
2123 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | ||
2124 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | ||
2125 | |||
2126 | if (!changed) | ||
2127 | return; | ||
2128 | |||
2129 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | ||
2130 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | ||
2131 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | ||
2132 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | ||
2133 | } | ||
2134 | |||
2098 | static void ilk_setup_wm_latency(struct drm_device *dev) | 2135 | static void ilk_setup_wm_latency(struct drm_device *dev) |
2099 | { | 2136 | { |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | 2137 | struct drm_i915_private *dev_priv = dev->dev_private; |
@@ -2112,6 +2149,9 @@ static void ilk_setup_wm_latency(struct drm_device *dev) | |||
2112 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | 2149 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
2113 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | 2150 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
2114 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | 2151 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
2152 | |||
2153 | if (IS_GEN6(dev)) | ||
2154 | snb_wm_latency_quirk(dev); | ||
2115 | } | 2155 | } |
2116 | 2156 | ||
2117 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, | 2157 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 6bc68bdcf433..79fb4cc2137c 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
@@ -437,32 +437,41 @@ static void ring_setup_phys_status_page(struct intel_ring_buffer *ring) | |||
437 | I915_WRITE(HWS_PGA, addr); | 437 | I915_WRITE(HWS_PGA, addr); |
438 | } | 438 | } |
439 | 439 | ||
440 | static int init_ring_common(struct intel_ring_buffer *ring) | 440 | static bool stop_ring(struct intel_ring_buffer *ring) |
441 | { | 441 | { |
442 | struct drm_device *dev = ring->dev; | 442 | struct drm_i915_private *dev_priv = to_i915(ring->dev); |
443 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
444 | struct drm_i915_gem_object *obj = ring->obj; | ||
445 | int ret = 0; | ||
446 | u32 head; | ||
447 | 443 | ||
448 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | 444 | if (!IS_GEN2(ring->dev)) { |
445 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | ||
446 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | ||
447 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | ||
448 | return false; | ||
449 | } | ||
450 | } | ||
449 | 451 | ||
450 | /* Stop the ring if it's running. */ | ||
451 | I915_WRITE_CTL(ring, 0); | 452 | I915_WRITE_CTL(ring, 0); |
452 | I915_WRITE_HEAD(ring, 0); | 453 | I915_WRITE_HEAD(ring, 0); |
453 | ring->write_tail(ring, 0); | 454 | ring->write_tail(ring, 0); |
454 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) | ||
455 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | ||
456 | 455 | ||
457 | if (I915_NEED_GFX_HWS(dev)) | 456 | if (!IS_GEN2(ring->dev)) { |
458 | intel_ring_setup_status_page(ring); | 457 | (void)I915_READ_CTL(ring); |
459 | else | 458 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); |
460 | ring_setup_phys_status_page(ring); | 459 | } |
461 | 460 | ||
462 | head = I915_READ_HEAD(ring) & HEAD_ADDR; | 461 | return (I915_READ_HEAD(ring) & HEAD_ADDR) == 0; |
462 | } | ||
463 | 463 | ||
464 | /* G45 ring initialization fails to reset head to zero */ | 464 | static int init_ring_common(struct intel_ring_buffer *ring) |
465 | if (head != 0) { | 465 | { |
466 | struct drm_device *dev = ring->dev; | ||
467 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
468 | struct drm_i915_gem_object *obj = ring->obj; | ||
469 | int ret = 0; | ||
470 | |||
471 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | ||
472 | |||
473 | if (!stop_ring(ring)) { | ||
474 | /* G45 ring initialization often fails to reset head to zero */ | ||
466 | DRM_DEBUG_KMS("%s head not reset to zero " | 475 | DRM_DEBUG_KMS("%s head not reset to zero " |
467 | "ctl %08x head %08x tail %08x start %08x\n", | 476 | "ctl %08x head %08x tail %08x start %08x\n", |
468 | ring->name, | 477 | ring->name, |
@@ -471,9 +480,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) | |||
471 | I915_READ_TAIL(ring), | 480 | I915_READ_TAIL(ring), |
472 | I915_READ_START(ring)); | 481 | I915_READ_START(ring)); |
473 | 482 | ||
474 | I915_WRITE_HEAD(ring, 0); | 483 | if (!stop_ring(ring)) { |
475 | |||
476 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { | ||
477 | DRM_ERROR("failed to set %s head to zero " | 484 | DRM_ERROR("failed to set %s head to zero " |
478 | "ctl %08x head %08x tail %08x start %08x\n", | 485 | "ctl %08x head %08x tail %08x start %08x\n", |
479 | ring->name, | 486 | ring->name, |
@@ -481,9 +488,16 @@ static int init_ring_common(struct intel_ring_buffer *ring) | |||
481 | I915_READ_HEAD(ring), | 488 | I915_READ_HEAD(ring), |
482 | I915_READ_TAIL(ring), | 489 | I915_READ_TAIL(ring), |
483 | I915_READ_START(ring)); | 490 | I915_READ_START(ring)); |
491 | ret = -EIO; | ||
492 | goto out; | ||
484 | } | 493 | } |
485 | } | 494 | } |
486 | 495 | ||
496 | if (I915_NEED_GFX_HWS(dev)) | ||
497 | intel_ring_setup_status_page(ring); | ||
498 | else | ||
499 | ring_setup_phys_status_page(ring); | ||
500 | |||
487 | /* Initialize the ring. This must happen _after_ we've cleared the ring | 501 | /* Initialize the ring. This must happen _after_ we've cleared the ring |
488 | * registers with the above sequence (the readback of the HEAD registers | 502 | * registers with the above sequence (the readback of the HEAD registers |
489 | * also enforces ordering), otherwise the hw might lose the new ring | 503 | * also enforces ordering), otherwise the hw might lose the new ring |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 270a6a973438..2b91c4b4d34b 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -34,6 +34,7 @@ struct intel_hw_status_page { | |||
34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | 34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) |
35 | 35 | ||
36 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) | 36 | #define I915_READ_MODE(ring) I915_READ(RING_MI_MODE((ring)->mmio_base)) |
37 | #define I915_WRITE_MODE(ring, val) I915_WRITE(RING_MI_MODE((ring)->mmio_base), val) | ||
37 | 38 | ||
38 | enum intel_ring_hangcheck_action { | 39 | enum intel_ring_hangcheck_action { |
39 | HANGCHECK_IDLE = 0, | 40 | HANGCHECK_IDLE = 0, |
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index d27155adf5db..46be00d66df3 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c | |||
@@ -2424,8 +2424,8 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, | |||
2424 | if (ret < 0) | 2424 | if (ret < 0) |
2425 | goto err1; | 2425 | goto err1; |
2426 | 2426 | ||
2427 | ret = sysfs_create_link(&encoder->ddc.dev.kobj, | 2427 | ret = sysfs_create_link(&drm_connector->kdev->kobj, |
2428 | &drm_connector->kdev->kobj, | 2428 | &encoder->ddc.dev.kobj, |
2429 | encoder->ddc.dev.kobj.name); | 2429 | encoder->ddc.dev.kobj.name); |
2430 | if (ret < 0) | 2430 | if (ret < 0) |
2431 | goto err2; | 2431 | goto err2; |
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index f729dc71d5be..d0c75779d3f6 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c | |||
@@ -185,6 +185,8 @@ static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |||
185 | { | 185 | { |
186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, | 186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
187 | _MASKED_BIT_DISABLE(0xffff)); | 187 | _MASKED_BIT_DISABLE(0xffff)); |
188 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, | ||
189 | _MASKED_BIT_DISABLE(0xffff)); | ||
188 | /* something from same cacheline, but !FORCEWAKE_VLV */ | 190 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
189 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); | 191 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
190 | } | 192 | } |