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authorDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-01 11:16:19 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-06-04 07:57:11 -0400
commit2bd89a07db684573d2fce0d5148103c3dcfb0873 (patch)
tree59bcc29e54c3f33073df335b9f5d49d043639614 /drivers/gpu/drm/i915
parentc0efc387a8893470c1744e775e214c069bd2465e (diff)
drm/i915: clear up the fdi dotclock semantics for M/N computation
We currently mutliply the link_bw of the fdi link with the pixel multiplier, which is wrong: The FDI link doesn't suddenly grow more bandwidth. In reality the pixel mutliplication only happens in the PCH, before the pixels are fed into the port. But since we our code treats the uses the target clock after pixels are doubled (tripled, ...) already, we need to correct this. Semantically it's clearer to divide the target clock to get the fdi dotclock instead of multiplying the bw, so do that instead. Note that the target clock is already multiplied by the same factor, so the division will never loose accuracy for the M/N computation. The lane computation otoh used the wrong value, we also need to feed the fdi dotclock to that. Split out on a request from Paulo Zanoni. v2: Also fix the lane computation, it used the target clock to compute the bw requirements, not the fdi dotclock (i.e. adjusted with the pixel multiplier). Since sdvo only uses the pixel multiplier for low-res modes (with a dotclock below 100MHz) we wouldn't ever have rejected a bogus mode, but just used an inefficient fdi config. v3: Amend the commit message to explain better what the change for the fdi lane config computation is all about. Requested by Paulo. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/intel_display.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index ed6addf74275..711ec3314893 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3989,7 +3989,7 @@ static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3989{ 3989{
3990 struct drm_device *dev = intel_crtc->base.dev; 3990 struct drm_device *dev = intel_crtc->base.dev;
3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; 3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992 int target_clock, lane, link_bw; 3992 int target_clock, lane, link_bw, fdi_dotclock;
3993 bool setup_ok, needs_recompute = false; 3993 bool setup_ok, needs_recompute = false;
3994 3994
3995retry: 3995retry:
@@ -4007,14 +4007,16 @@ retry:
4007 else 4007 else
4008 target_clock = adjusted_mode->clock; 4008 target_clock = adjusted_mode->clock;
4009 4009
4010 lane = ironlake_get_lanes_required(target_clock, link_bw, 4010 fdi_dotclock = target_clock;
4011 if (pipe_config->pixel_multiplier > 1)
4012 fdi_dotclock /= pipe_config->pixel_multiplier;
4013
4014 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4011 pipe_config->pipe_bpp); 4015 pipe_config->pipe_bpp);
4012 4016
4013 pipe_config->fdi_lanes = lane; 4017 pipe_config->fdi_lanes = lane;
4014 4018
4015 if (pipe_config->pixel_multiplier > 1) 4019 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4016 link_bw *= pipe_config->pixel_multiplier;
4017 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4018 link_bw, &pipe_config->fdi_m_n); 4020 link_bw, &pipe_config->fdi_m_n);
4019 4021
4020 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, 4022 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,