diff options
author | Kristian Høgsberg <krh@bitplanet.net> | 2009-10-19 14:35:30 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2009-11-05 17:47:13 -0500 |
commit | a4f45cf178f0d0ad4e516e020818b5f1c00e3d63 (patch) | |
tree | ab135d480b0f9d8b3e9c4b94216c647a840c30e0 /drivers/gpu/drm/i915 | |
parent | f3cd474bb235f2331c1a6f579bdbf892386e5c7c (diff) |
drm/i915: Support 30 bit depth modes
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index d1be1849580d..e8c6d00cde97 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -1915,6 +1915,7 @@ | |||
1915 | #define DISPPLANE_16BPP (0x5<<26) | 1915 | #define DISPPLANE_16BPP (0x5<<26) |
1916 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) | 1916 | #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) |
1917 | #define DISPPLANE_32BPP (0x7<<26) | 1917 | #define DISPPLANE_32BPP (0x7<<26) |
1918 | #define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26) | ||
1918 | #define DISPPLANE_STEREO_ENABLE (1<<25) | 1919 | #define DISPPLANE_STEREO_ENABLE (1<<25) |
1919 | #define DISPPLANE_STEREO_DISABLE 0 | 1920 | #define DISPPLANE_STEREO_DISABLE 0 |
1920 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) | 1921 | #define DISPPLANE_SEL_PIPE_MASK (1<<24) |
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8df81401c149..e4221b8844ce 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1289,7 +1289,10 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, | |||
1289 | break; | 1289 | break; |
1290 | case 24: | 1290 | case 24: |
1291 | case 32: | 1291 | case 32: |
1292 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | 1292 | if (crtc->fb->depth == 30) |
1293 | dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA; | ||
1294 | else | ||
1295 | dspcntr |= DISPPLANE_32BPP_NO_ALPHA; | ||
1293 | break; | 1296 | break; |
1294 | default: | 1297 | default: |
1295 | DRM_ERROR("Unknown color depth\n"); | 1298 | DRM_ERROR("Unknown color depth\n"); |