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authorChris Wilson <chris@chris-wilson.co.uk>2010-08-12 04:42:51 -0400
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-08 05:23:42 -0400
commit31578148b2c62612f9516fdcf5ebb64ab32ed12d (patch)
tree0ed59f332fc2b02088dc17511ff0b4808502bbd5 /drivers/gpu/drm/i915
parent0ddc1289f3ffd779779ddd3922f26ae7d0a21604 (diff)
drm/i915/overlay: Move capabilities bits to common info block.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c12
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h5
-rw-r--r--drivers/gpu/drm/i915/intel_overlay.c40
3 files changed, 36 insertions, 21 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2879a768d65c..dffc1bcf7b79 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -62,49 +62,60 @@ extern int intel_agp_enabled;
62 62
63static const struct intel_device_info intel_i830_info = { 63static const struct intel_device_info intel_i830_info = {
64 .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1, 64 .gen = 2, .is_i8xx = 1, .is_mobile = 1, .cursor_needs_physical = 1,
65 .has_overlay = 1, .overlay_needs_physical = 1,
65}; 66};
66 67
67static const struct intel_device_info intel_845g_info = { 68static const struct intel_device_info intel_845g_info = {
68 .gen = 2, .is_i8xx = 1, 69 .gen = 2, .is_i8xx = 1,
70 .has_overlay = 1, .overlay_needs_physical = 1,
69}; 71};
70 72
71static const struct intel_device_info intel_i85x_info = { 73static const struct intel_device_info intel_i85x_info = {
72 .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1, 74 .gen = 2, .is_i8xx = 1, .is_i85x = 1, .is_mobile = 1,
73 .cursor_needs_physical = 1, 75 .cursor_needs_physical = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
74}; 77};
75 78
76static const struct intel_device_info intel_i865g_info = { 79static const struct intel_device_info intel_i865g_info = {
77 .gen = 2, .is_i8xx = 1, 80 .gen = 2, .is_i8xx = 1,
81 .has_overlay = 1, .overlay_needs_physical = 1,
78}; 82};
79 83
80static const struct intel_device_info intel_i915g_info = { 84static const struct intel_device_info intel_i915g_info = {
81 .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1, 85 .gen = 3, .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
86 .has_overlay = 1, .overlay_needs_physical = 1,
82}; 87};
83static const struct intel_device_info intel_i915gm_info = { 88static const struct intel_device_info intel_i915gm_info = {
84 .gen = 3, .is_i9xx = 1, .is_mobile = 1, 89 .gen = 3, .is_i9xx = 1, .is_mobile = 1,
85 .cursor_needs_physical = 1, 90 .cursor_needs_physical = 1,
91 .has_overlay = 1, .overlay_needs_physical = 1,
86}; 92};
87static const struct intel_device_info intel_i945g_info = { 93static const struct intel_device_info intel_i945g_info = {
88 .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1, 94 .gen = 3, .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
95 .has_overlay = 1, .overlay_needs_physical = 1,
89}; 96};
90static const struct intel_device_info intel_i945gm_info = { 97static const struct intel_device_info intel_i945gm_info = {
91 .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, 98 .gen = 3, .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
92 .has_hotplug = 1, .cursor_needs_physical = 1, 99 .has_hotplug = 1, .cursor_needs_physical = 1,
100 .has_overlay = 1, .overlay_needs_physical = 1,
93}; 101};
94 102
95static const struct intel_device_info intel_i965g_info = { 103static const struct intel_device_info intel_i965g_info = {
96 .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1, 104 .gen = 4, .is_broadwater = 1, .is_i965g = 1, .is_i9xx = 1,
97 .has_hotplug = 1, 105 .has_hotplug = 1,
106 .has_overlay = 1,
98}; 107};
99 108
100static const struct intel_device_info intel_i965gm_info = { 109static const struct intel_device_info intel_i965gm_info = {
101 .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1, 110 .gen = 4, .is_crestline = 1, .is_i965g = 1, .is_i965gm = 1, .is_i9xx = 1,
102 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1, 111 .is_mobile = 1, .has_fbc = 1, .has_rc6 = 1, .has_hotplug = 1,
112 .has_overlay = 1,
103}; 113};
104 114
105static const struct intel_device_info intel_g33_info = { 115static const struct intel_device_info intel_g33_info = {
106 .gen = 3, .is_g33 = 1, .is_i9xx = 1, 116 .gen = 3, .is_g33 = 1, .is_i9xx = 1,
107 .need_gfx_hws = 1, .has_hotplug = 1, 117 .need_gfx_hws = 1, .has_hotplug = 1,
118 .has_overlay = 1,
108}; 119};
109 120
110static const struct intel_device_info intel_g45_info = { 121static const struct intel_device_info intel_g45_info = {
@@ -121,6 +132,7 @@ static const struct intel_device_info intel_gm45_info = {
121static const struct intel_device_info intel_pineview_info = { 132static const struct intel_device_info intel_pineview_info = {
122 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1, 133 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .is_i9xx = 1,
123 .need_gfx_hws = 1, .has_hotplug = 1, 134 .need_gfx_hws = 1, .has_hotplug = 1,
135 .has_overlay = 1,
124}; 136};
125 137
126static const struct intel_device_info intel_ironlake_d_info = { 138static const struct intel_device_info intel_ironlake_d_info = {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f983130a702d..10c9e416c96b 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -213,6 +213,8 @@ struct intel_device_info {
213 u8 has_pipe_cxsr : 1; 213 u8 has_pipe_cxsr : 1;
214 u8 has_hotplug : 1; 214 u8 has_hotplug : 1;
215 u8 cursor_needs_physical : 1; 215 u8 cursor_needs_physical : 1;
216 u8 has_overlay : 1;
217 u8 overlay_needs_physical : 1;
216}; 218};
217 219
218enum no_fbc_reason { 220enum no_fbc_reason {
@@ -1218,6 +1220,9 @@ static inline void i915_write(struct drm_i915_private *dev_priv, u32 reg,
1218#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev)) 1220#define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1219#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) 1221#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1220 1222
1223#define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1224#define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1225
1221/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte 1226/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1222 * rows, which changed the alignment requirements and fence programming. 1227 * rows, which changed the alignment requirements and fence programming.
1223 */ 1228 */
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index fef4dd61dcfd..df5277aaa98b 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -173,9 +173,6 @@ struct overlay_registers {
173/* overlay flip addr flag */ 173/* overlay flip addr flag */
174#define OFC_UPDATE 0x1 174#define OFC_UPDATE 0x1
175 175
176#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
177#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
178
179static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay) 176static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
180{ 177{
181 drm_i915_private_t *dev_priv = overlay->dev->dev_private; 178 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
@@ -184,7 +181,9 @@ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_over
184 /* no recursive mappings */ 181 /* no recursive mappings */
185 BUG_ON(overlay->virt_addr); 182 BUG_ON(overlay->virt_addr);
186 183
187 if (OVERLAY_NONPHYSICAL(overlay->dev)) { 184 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
185 regs = overlay->reg_bo->phys_obj->handle->vaddr;
186 } else {
188 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, 187 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
189 overlay->reg_bo->gtt_offset, 188 overlay->reg_bo->gtt_offset,
190 KM_USER0); 189 KM_USER0);
@@ -193,15 +192,14 @@ static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_over
193 DRM_ERROR("failed to map overlay regs in GTT\n"); 192 DRM_ERROR("failed to map overlay regs in GTT\n");
194 return NULL; 193 return NULL;
195 } 194 }
196 } else 195 }
197 regs = overlay->reg_bo->phys_obj->handle->vaddr;
198 196
199 return overlay->virt_addr = regs; 197 return overlay->virt_addr = regs;
200} 198}
201 199
202static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay) 200static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
203{ 201{
204 if (OVERLAY_NONPHYSICAL(overlay->dev)) 202 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
205 io_mapping_unmap_atomic(overlay->virt_addr, KM_USER0); 203 io_mapping_unmap_atomic(overlay->virt_addr, KM_USER0);
206 204
207 overlay->virt_addr = NULL; 205 overlay->virt_addr = NULL;
@@ -1366,7 +1364,7 @@ void intel_setup_overlay(struct drm_device *dev)
1366 struct overlay_registers *regs; 1364 struct overlay_registers *regs;
1367 int ret; 1365 int ret;
1368 1366
1369 if (!OVERLAY_EXISTS(dev)) 1367 if (!HAS_OVERLAY(dev))
1370 return; 1368 return;
1371 1369
1372 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL); 1370 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
@@ -1379,7 +1377,16 @@ void intel_setup_overlay(struct drm_device *dev)
1379 goto out_free; 1377 goto out_free;
1380 overlay->reg_bo = to_intel_bo(reg_bo); 1378 overlay->reg_bo = to_intel_bo(reg_bo);
1381 1379
1382 if (OVERLAY_NONPHYSICAL(dev)) { 1380 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1381 ret = i915_gem_attach_phys_object(dev, reg_bo,
1382 I915_GEM_PHYS_OVERLAY_REGS,
1383 0);
1384 if (ret) {
1385 DRM_ERROR("failed to attach phys overlay regs\n");
1386 goto out_free_bo;
1387 }
1388 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1389 } else {
1383 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE); 1390 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1384 if (ret) { 1391 if (ret) {
1385 DRM_ERROR("failed to pin overlay register bo\n"); 1392 DRM_ERROR("failed to pin overlay register bo\n");
@@ -1392,15 +1399,6 @@ void intel_setup_overlay(struct drm_device *dev)
1392 DRM_ERROR("failed to move overlay register bo into the GTT\n"); 1399 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1393 goto out_unpin_bo; 1400 goto out_unpin_bo;
1394 } 1401 }
1395 } else {
1396 ret = i915_gem_attach_phys_object(dev, reg_bo,
1397 I915_GEM_PHYS_OVERLAY_REGS,
1398 0);
1399 if (ret) {
1400 DRM_ERROR("failed to attach phys overlay regs\n");
1401 goto out_free_bo;
1402 }
1403 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1404 } 1402 }
1405 1403
1406 /* init all values */ 1404 /* init all values */
@@ -1471,10 +1469,10 @@ intel_overlay_capture_error_state(struct drm_device *dev)
1471 1469
1472 error->dovsta = I915_READ(DOVSTA); 1470 error->dovsta = I915_READ(DOVSTA);
1473 error->isr = I915_READ(ISR); 1471 error->isr = I915_READ(ISR);
1474 if (OVERLAY_NONPHYSICAL(overlay->dev)) 1472 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1475 error->base = (long) overlay->reg_bo->gtt_offset;
1476 else
1477 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr; 1473 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1474 else
1475 error->base = (long) overlay->reg_bo->gtt_offset;
1478 1476
1479 regs = intel_overlay_map_regs_atomic(overlay); 1477 regs = intel_overlay_map_regs_atomic(overlay);
1480 if (!regs) 1478 if (!regs)