diff options
author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2010-06-30 16:16:00 -0400 |
---|---|---|
committer | Eric Anholt <eric@anholt.net> | 2010-08-01 22:03:42 -0400 |
commit | d874bcff793d6167c8aa3dd0c2fd00ca40ab12a2 (patch) | |
tree | 802d472d0f4700d91809af66cb1853afa9078d27 /drivers/gpu/drm/i915 | |
parent | e25e6601099d6d8e5a2221e47cdd142814616b08 (diff) |
drm/i915: remove duplicate PIPE*STAT bit definitions
Having two sets has made me think I caught a bug more than once now.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 12 | ||||
-rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 26 |
2 files changed, 6 insertions, 32 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 390d111dc45e..fb6b46285471 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c | |||
@@ -171,10 +171,10 @@ void intel_enable_asle (struct drm_device *dev) | |||
171 | ironlake_enable_display_irq(dev_priv, DE_GSE); | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
172 | else { | 172 | else { |
173 | i915_enable_pipestat(dev_priv, 1, | 173 | i915_enable_pipestat(dev_priv, 1, |
174 | I915_LEGACY_BLC_EVENT_ENABLE); | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
175 | if (IS_I965G(dev)) | 175 | if (IS_I965G(dev)) |
176 | i915_enable_pipestat(dev_priv, 0, | 176 | i915_enable_pipestat(dev_priv, 0, |
177 | I915_LEGACY_BLC_EVENT_ENABLE); | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
178 | } | 178 | } |
179 | } | 179 | } |
180 | 180 | ||
@@ -856,9 +856,9 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
856 | iir = I915_READ(IIR); | 856 | iir = I915_READ(IIR); |
857 | 857 | ||
858 | if (IS_I965G(dev)) | 858 | if (IS_I965G(dev)) |
859 | vblank_status = I915_START_VBLANK_INTERRUPT_STATUS; | 859 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
860 | else | 860 | else |
861 | vblank_status = I915_VBLANK_INTERRUPT_STATUS; | 861 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
862 | 862 | ||
863 | for (;;) { | 863 | for (;;) { |
864 | irq_received = iir != 0; | 864 | irq_received = iir != 0; |
@@ -962,8 +962,8 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) | |||
962 | intel_finish_page_flip(dev, 1); | 962 | intel_finish_page_flip(dev, 1); |
963 | } | 963 | } |
964 | 964 | ||
965 | if ((pipea_stats & I915_LEGACY_BLC_EVENT_STATUS) || | 965 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
966 | (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) || | 966 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
967 | (iir & I915_ASLE_INTERRUPT)) | 967 | (iir & I915_ASLE_INTERRUPT)) |
968 | opregion_asle_intr(dev); | 968 | opregion_asle_intr(dev); |
969 | 969 | ||
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6d9b0288272a..dc7c6f8c6693 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
@@ -595,32 +595,6 @@ | |||
595 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ | 595 | #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ |
596 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ | 596 | #define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */ |
597 | 597 | ||
598 | #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) | ||
599 | #define I915_CRC_ERROR_ENABLE (1UL<<29) | ||
600 | #define I915_CRC_DONE_ENABLE (1UL<<28) | ||
601 | #define I915_GMBUS_EVENT_ENABLE (1UL<<27) | ||
602 | #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) | ||
603 | #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) | ||
604 | #define I915_DPST_EVENT_ENABLE (1UL<<23) | ||
605 | #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) | ||
606 | #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) | ||
607 | #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) | ||
608 | #define I915_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ | ||
609 | #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) | ||
610 | #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) | ||
611 | #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) | ||
612 | #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) | ||
613 | #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) | ||
614 | #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) | ||
615 | #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) | ||
616 | #define I915_DPST_EVENT_STATUS (1UL<<7) | ||
617 | #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) | ||
618 | #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) | ||
619 | #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) | ||
620 | #define I915_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ | ||
621 | #define I915_VBLANK_INTERRUPT_STATUS (1UL<<1) | ||
622 | #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) | ||
623 | |||
624 | #define SRX_INDEX 0x3c4 | 598 | #define SRX_INDEX 0x3c4 |
625 | #define SRX_DATA 0x3c5 | 599 | #define SRX_DATA 0x3c5 |
626 | #define SR01 1 | 600 | #define SR01 1 |