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authorBen Widawsky <ben@bwidawsk.net>2013-07-05 17:41:04 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-07-08 16:04:34 -0400
commitf343c5f6477354967ee1e331a68a56b9fece2f36 (patch)
tree71bcf1f5c511b3fa13369badf81e074d8d603543 /drivers/gpu/drm/i915/intel_sprite.c
parent338710e7aff3428dc8170a03704a8ae981b58dcd (diff)
drm/i915: Getter/setter for object attributes
Soon we want to gut a lot of our existing assumptions how many address spaces an object can live in, and in doing so, embed the drm_mm_node in the object (and later the VMA). It's possible in the future we'll want to add more getter/setter methods, but for now this is enough to enable the VMAs. v2: Reworked commit message (Ben) Added comments to the main functions (Ben) sed -i "s/i915_gem_obj_set_color/i915_gem_obj_ggtt_set_color/" drivers/gpu/drm/i915/*.[ch] sed -i "s/i915_gem_obj_bound/i915_gem_obj_ggtt_bound/" drivers/gpu/drm/i915/*.[ch] sed -i "s/i915_gem_obj_size/i915_gem_obj_ggtt_size/" drivers/gpu/drm/i915/*.[ch] sed -i "s/i915_gem_obj_offset/i915_gem_obj_ggtt_offset/" drivers/gpu/drm/i915/*.[ch] (Daniel) v3: Rebased on new reserve_node patch Changed DRM_DEBUG_KMS to actually work (will need fixing later) Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 1fa5612a4572..55bdf70b548b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -133,7 +133,7 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_framebuffer *fb,
133 133
134 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w); 134 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
135 I915_WRITE(SPCNTR(pipe, plane), sprctl); 135 I915_WRITE(SPCNTR(pipe, plane), sprctl);
136 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), obj->gtt_offset + 136 I915_MODIFY_DISPBASE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
137 sprsurf_offset); 137 sprsurf_offset);
138 POSTING_READ(SPSURF(pipe, plane)); 138 POSTING_READ(SPSURF(pipe, plane));
139} 139}
@@ -308,7 +308,8 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
308 if (intel_plane->can_scale) 308 if (intel_plane->can_scale)
309 I915_WRITE(SPRSCALE(pipe), sprscale); 309 I915_WRITE(SPRSCALE(pipe), sprscale);
310 I915_WRITE(SPRCTL(pipe), sprctl); 310 I915_WRITE(SPRCTL(pipe), sprctl);
311 I915_MODIFY_DISPBASE(SPRSURF(pipe), obj->gtt_offset + sprsurf_offset); 311 I915_MODIFY_DISPBASE(SPRSURF(pipe),
312 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
312 POSTING_READ(SPRSURF(pipe)); 313 POSTING_READ(SPRSURF(pipe));
313 314
314 /* potentially re-enable LP watermarks */ 315 /* potentially re-enable LP watermarks */
@@ -478,7 +479,8 @@ ilk_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
478 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 479 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
479 I915_WRITE(DVSSCALE(pipe), dvsscale); 480 I915_WRITE(DVSSCALE(pipe), dvsscale);
480 I915_WRITE(DVSCNTR(pipe), dvscntr); 481 I915_WRITE(DVSCNTR(pipe), dvscntr);
481 I915_MODIFY_DISPBASE(DVSSURF(pipe), obj->gtt_offset + dvssurf_offset); 482 I915_MODIFY_DISPBASE(DVSSURF(pipe),
483 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
482 POSTING_READ(DVSSURF(pipe)); 484 POSTING_READ(DVSSURF(pipe));
483} 485}
484 486