diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2010-08-02 11:06:59 -0400 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2010-09-21 06:20:04 -0400 |
commit | 7f2ab69913135f0377a1dfc1da5695b64107d3ca (patch) | |
tree | a77229702de475d9184d78593aefc7bb2795ca5e /drivers/gpu/drm/i915/intel_ringbuffer.h | |
parent | 570ef608591aa1c7f7cb615c2d33b30246179da1 (diff) |
drm/i915: use new macros to access the ring ctl register
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.h')
-rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index af09eaa84bed..1668cd9ac876 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h | |||
@@ -13,6 +13,8 @@ struct intel_hw_status_page { | |||
13 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) | 13 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START(ring->mmio_base), val) |
14 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base)) | 14 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD(ring->mmio_base)) |
15 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) | 15 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD(ring->mmio_base), val) |
16 | #define I915_READ_CTL(ring) I915_READ(RING_CTL(ring->mmio_base)) | ||
17 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL(ring->mmio_base), val) | ||
16 | 18 | ||
17 | struct drm_i915_gem_execbuffer2; | 19 | struct drm_i915_gem_execbuffer2; |
18 | struct intel_ring_buffer { | 20 | struct intel_ring_buffer { |
@@ -21,9 +23,6 @@ struct intel_ring_buffer { | |||
21 | RING_RENDER = 0x1, | 23 | RING_RENDER = 0x1, |
22 | RING_BSD = 0x2, | 24 | RING_BSD = 0x2, |
23 | } id; | 25 | } id; |
24 | struct ring_regs { | ||
25 | u32 ctl; | ||
26 | } regs; | ||
27 | u32 mmio_base; | 26 | u32 mmio_base; |
28 | unsigned long size; | 27 | unsigned long size; |
29 | unsigned int alignment; | 28 | unsigned int alignment; |